[Bug rtl-optimization/68991] -O3 generates misaligned xorv4si3

[hjl.tools at gmail dot com]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=68991

H.J. Lu <hjl.tools at gmail dot com> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
             Target|x32                         |x86
             Status|UNCONFIRMED                 |NEW
   Last reconfirmed|                            |2015-12-18
                 CC|                            |ubizjak at gmail dot com
     Ever confirmed|0                           |1

--- Comment #1 from H.J. Lu <hjl.tools at gmail dot com> ---
You can't combine

(insn 438 191 193 22 (set (reg:V4SI 326)
        (subreg:V4SI (reg:TI 245 [ MEM[(const struct bitset &)FeatureEntry_21 +
8] ]) 0)) /usr/include/c++/5.3.1/bitset:1139 -1
     (expr_list:REG_DEAD (reg:TI 245 [ MEM[(const struct bitset
&)FeatureEntry_21 + 8] ])
        (nil)))

(insn 194 193 439 22 (set (reg:V4SI 246 [ vect__45.575 ])
        (xor:V4SI (reg:V4SI 326)
            (reg:V4SI 247))) /usr/include/c++/5.3.1/bitset:163 3433 {*xorv4si3}
     (expr_list:REG_DEAD (reg:V4SI 326)
        (expr_list:REG_DEAD (reg:V4SI 247)
            (expr_list:REG_EQUAL (not:V4SI (mem/c:V4SI (plus:SI (reg/f:SI 20
frame)
                            (const_int -32 [0xffffffffffffffe0])) [14 MEM[(long
unsigned int *)&D.120283]+0 S16 A128]))
                (nil)))))

into

(insn 194 193 439 22 (set (reg:V4SI 246 [ vect__45.575 ])
        (xor:V4SI (reg:V4SI 247)
            (subreg:V4SI (reg:TI 245 [ MEM[(const struct bitset
&)FeatureEntry_21 + 8] ]) 0))) /usr/include/c++/5.3.1/bitset:163 3433
{*xorv4si3}
     (expr_list:REG_DEAD (reg:TI 245 [ MEM[(const struct bitset
&)FeatureEntry_21 + 8] ])
        (expr_list:REG_DEAD (reg:V4SI 247)
            (nil))))

for SSE.