https://gcc.gnu.org/bugzilla/show_bug.cgi?id=67291
--- Comment #4 from Michael Meissner <meissner at gcc dot gnu.org> ---
Ww is the wrong constraint to use for this instruction. The ww constraint is
intended to be used with the VSX scalar single precision floating point
instructions added in ISA 2.07 (i.e. power8). On ISA 2.06 (i.e. power7), ww
becomes NO_REGS, because that machine did not provide those instructions. This
is so we can encode SFmode operations in one insn. Here is a simplification of
the add insn for single precision floating point to show how ww is used:
(define_insn "addsf3"
[(set (match_operand:SF 0 "register_operand" "=f,ww")
(plus:SF (match_operand:SF 1 "register_operand" "f,ww")
(match_operand:SF 2 "register_opreand" "f,ww")]
"..."
"@
fadds %0,%1,%2
xsaddsp %x0,%x1,%x2")
The appropriate constraint for vector float is "wf" (you can use "wa" which is
the constraint for all VSX registers, since we map "wf" and "wd" to "wa").
There is no constraint that targets integer vectors specifically. If you are
using a VSX instruction you want the "wa" constraint (instructions with a "xs"
or "xv" prefix). If you are using an Altivec instruction (typically
instructions with a "v" prefix) you want to use "v".
