https://gcc.gnu.org/bugzilla/show_bug.cgi?id=66410
--- Comment #1 from Kazumoto Kojima <kkojima at gcc dot gnu.org> --- Created attachment 35694 --> https://gcc.gnu.org/bugzilla/attachment.cgi?id=35694&action=edit reduced test case Here is a part of .reload for this test case which shows what is going on: Choosing alt 3 in insn 52: (0) Snd (1) r {*movhi} Creating newreg=276, assigning class GENERAL_REGS to r276 52: [r193:SI+r275:SI]=r276:HI Inserting insn reload before: 298: r275:SI=r196:SI 299: r276:HI=r190:SI#0 Creating newreg=277, assigning class R0_REGS to secondary r277 299: r276:HI=r190:SI#0 Inserting the move before: 300: r277:HI=r190:SI#0 It seems that LRA chooses R0_REGS for reloading the source reg of this *movhi insn and it causes the problem. One idea is to disparage the use of r0 for that case with '^' modifier of constrains in *movhi. I'm testing the patch below. diff --git a/config/sh/constraints.md b/config/sh/constraints.md index bd059a4..cd9146d 100644 --- a/config/sh/constraints.md +++ b/config/sh/constraints.md @@ -309,6 +309,19 @@ (and (match_code "mem") (match_test "! satisfies_constraint_Sdd (op)"))) +(define_memory_constraint "Sid" + "A memory reference that uses index addressing." + (and (match_code "mem") + (match_code "plus" "0") + (match_code "reg" "00") + (match_code "reg" "01"))) + +(define_memory_constraint "Ssd" + "A memory reference that uses simple register addressing." + (and (match_code "mem") + (match_test "! satisfies_constraint_Sid (op)") + (match_test "! satisfies_constraint_Sdd (op)"))) + (define_memory_constraint "Sbv" "A memory reference, as used in SH2A bclr.b, bset.b, etc." (and (match_test "MEM_P (op) && GET_MODE (op) == QImode") diff --git a/config/sh/sh.md b/config/sh/sh.md index 634a612..33241a8 100644 --- a/config/sh/sh.md +++ b/config/sh/sh.md @@ -7430,18 +7430,18 @@ label: ;; Q/r has to come first, otherwise PC relative loads might wrongly get ;; placed into delay slots. Since there is no QImode PC relative load, the ;; Q constraint and general_movsrc_operand will reject it for QImode. -;; The Snd alternatives should come before Sdd in order to avoid a preference -;; of using r0 als the register operand for addressing modes other than -;; displacement addressing. +;; The Sid/Ssd alternatives should come before Sdd in order to avoid +;; a preference of using r0 als the register operand for addressing modes +;; other than displacement addressing. Sid/z is disparaged by '^'. ;; The Sdd alternatives allow only r0 as register operand, even though on ;; SH2A any register could be allowed by switching to a 32 bit insn. ;; Generally sticking to the r0 is preferrable, since it generates smaller ;; code. Obvious r0 reloads can then be eliminated with a peephole on SH2A. (define_insn "*mov<mode>" [(set (match_operand:QIHI 0 "general_movdst_operand" - "=r,r,r,Snd,r, Sdd,z, r,l") + "=r,r,r,Sid,^zr,Ssd,r, Sdd,z, r,l") (match_operand:QIHI 1 "general_movsrc_operand" - "Q,r,i,r, Snd,z, Sdd,l,r"))] + "Q,r,i,^zr,Sid,r, Ssd,z, Sdd,l,r"))] "TARGET_SH1 && (arith_reg_operand (operands[0], <MODE>mode) || arith_reg_operand (operands[1], <MODE>mode))" @@ -7453,9 +7453,11 @@ label: mov.<bw> %1,%0 mov.<bw> %1,%0 mov.<bw> %1,%0 + mov.<bw> %1,%0 + mov.<bw> %1,%0 sts %1,%0 lds %1,%0" - [(set_attr "type" "pcload,move,movi8,store,load,store,load,prget,prset") + [(set_attr "type" "pcload,move,movi8,store,load,store,load,store,load,prget,prset") (set (attr "length") (cond [(and (match_operand 0 "displacement_mem_operand") (not (match_operand 0 "short_displacement_mem_operand")))
