https://gcc.gnu.org/bugzilla/show_bug.cgi?id=65212
Bug ID: 65212
Summary: --with-arch=nocona and -msse3
Product: gcc
Version: 4.9.2
Status: UNCONFIRMED
Severity: normal
Priority: P3
Component: target
Assignee: unassigned at gcc dot gnu.org
Reporter: dilyan.palauzov at aegee dot org
At
https://gcc.gnu.org/onlinedocs/gcc-4.9.2/gcc/i386-and-x86-64-Options.html#i386-and-x86-64-Options
is written:
‘nocona’
Improved version of Intel Pentium 4 CPU with 64-bit extensions, MMX, SSE,
SSE2 and SSE3 instruction set support.
I ./configure gcc with --with-arch=nocona, and running afterwards
`gcc -Q --help=target` I get (among other things):
-march= nocona
-mmmx [disabled]
-msse [disabled]
-msse2 [disabled]
-msse2avx [disabled]
-msse3 [disabled]
Provided that gcc is instructed to generate code for Intel Nocona, which has
SSE3, why is the -msse3 directive not enabled automatically?
I expect here to have SSE2 enabled automatically, as under this circumstances
(code for Nocona) I do not see a point to disable it.
