https://gcc.gnu.org/bugzilla/show_bug.cgi?id=63965
--- Comment #6 from Michael Meissner <meissner at gcc dot gnu.org> --- Author: meissner Date: Fri Nov 21 18:03:09 2014 New Revision: 217940 URL: https://gcc.gnu.org/viewcvs?rev=217940&root=gcc&view=rev Log: 2014-11-21 Michael Meissner <meiss...@linux.vnet.ibm.com> PR target/63965 * config/rs6000/rs6000.c (rs6000_setup_reg_addr_masks): Do not set Altivec & -16 mask if the type is not valid for Altivec registers. (rs6000_secondary_reload_memory): Add support for ((reg + const) + reg) that occurs during push_reload processing. * config/rs6000/altivec.md (altivec_mov<mode>): Add instruction alternative for moving constant vectors which are easy altivec constants to GPRs. Set the length attribute each of the alternatives. Modified: trunk/gcc/ChangeLog trunk/gcc/config/rs6000/rs6000-cpus.def trunk/gcc/config/rs6000/rs6000.c
