https://gcc.gnu.org/bugzilla/show_bug.cgi?id=63620
Uroš Bizjak <ubizjak at gmail dot com> changed:
What |Removed |Added
----------------------------------------------------------------------------
Keywords| |ra
Target|Darwin |x86
Status|UNCONFIRMED |NEW
Last reconfirmed| |2014-10-26
Target Milestone|--- |5.0
Ever confirmed|0 |1
--- Comment #3 from Uroš Bizjak <ubizjak at gmail dot com> ---
Confirmed. This will affect all SSE targets.
This is an RA issue. When RA kicks the constant to a memory, PIC register
should be marked as live for the insn that accesses memory.
We start with:
(insn 21 17 22 3 (set (mem:TF (pre_dec:SI (reg/f:SI 7 sp)) [1 S16 A128])
(const_double:TF 1.0e+29 [0x0.a18f07d736b90be55p+97])) pr63620.c:21 121
{*pushtf}
(expr_list:REG_ARGS_SIZE (const_int 16 [0x10])
(nil)))
and RA does:
Choosing alt 0 in insn 21: (0) =< (1) x {*pushtf}
Creating newreg=93, assigning class GENERAL_REGS to addr r93
Change to class INDEX_REGS for r93
Creating newreg=94, assigning class SSE_REGS to r94
21: [--sp:SI]=r94:TF
REG_ARGS_SIZE 0x10
Inserting insn reload before:
46: r93:SI=r87:SI+const(unspec[`*LC0'] 10)
REG_EQUAL `*LC0'
47: r94:TF=[r93:SI]
which results in:
(insn 46 17 47 3 (set (reg:SI 0 ax [93])
(plus:SI (reg:SI 0 ax [87])
(const:SI (unspec:SI [
(symbol_ref/u:SI ("*LC0") [flags 0x2])
] UNSPEC_MACHOPIC_OFFSET)))) pr63620.c:21 213 {*leasi}
(expr_list:REG_EQUAL (symbol_ref/u:SI ("*LC0") [flags 0x2])
(nil)))
(insn 47 46 21 3 (set (reg:TF 23 xmm2 [94])
(mem/u/c:TF (reg:SI 0 ax [93]) [1 S16 A128])) pr63620.c:21 126
{*movtf_internal}
(nil))
(insn 21 47 22 3 (set (mem:TF (pre_dec:SI (reg/f:SI 7 sp)) [1 S16 A128])
(reg:TF 23 xmm2 [94])) pr63620.c:21 121 {*pushtf}
(expr_list:REG_ARGS_SIZE (const_int 16 [0x10])
(nil)))
When the constant is pushed to a memory to satisfy operand constraints, the PIC
register should be marked as live (== used by the insn that reads memory). RA
even sets the REG_EQUAL to a symbol_ref in the reloading insn.
The patch at Comment #2 will just paper over the issue.
