https://gcc.gnu.org/bugzilla/show_bug.cgi?id=62308
--- Comment #7 from Venkataramanan <venkataramanan.kumar at amd dot com> ---
I tried to look at the RTL and assembly code generated after the patch comitted
in 215707.
The code generated looks good some unoptimal code but it is at -O0.
sub sp, sp, #16 // 15 *adddi3_aarch64/3 [length = 4]
mov x2, x0 // 2 *movdi_aarch64/1 [length = 4]
mov x0, x2 // 5 *movdi_aarch64/1 [length = 4]
fmov d0, x1 // 22 move_lo_quad_internal_be_v4si/2 [length = 4]
ins v0.d[1], x0 // 23 aarch64_simd_move_hi_quad_be_v4si/2
[length = 4]
str q0, [sp] // 7 *aarch64_simd_movv4si/2 [length = 4]
nop // 13 nop [length = 4]
add sp, sp, 16 // 18 *adddi3_aarch64/1 [length = 4]
ret // 20 *do_return [length = 4]
The patch r215707 tries to fix situation where paradoxial subregister access
with register X0 results results in acessing register -1 in bigendian.
The same situation happens for this bug.
insn 3 2 4 2 (set (reg:DI 76)
(reg:DI 1 x1 [ args+8 ])) test.c:3 35 {*movdi_aarch64}
(expr_list:REG_DEAD (reg:DI 1 x1 [ args+8 ])
(nil)))
(insn 4 3 5 2 (set (reg:TI 74)
(subreg:TI (reg:DI 76) 0)) test.c:3 38 {*movti_aarch64}
(expr_list:REG_DEAD (reg:DI 76)
(nil)))
Where reload gets
(set (reg:DI 0 x0 [76]) (reg:DI 1 x1 [ args+8 ]))
(set (reg:TI 0 x0 [74]) (reg:TI -1 [+-8 ])
Looks same issue to me.
Vladimir can you please confirm.
