http://gcc.gnu.org/bugzilla/show_bug.cgi?id=59985
Bug ID: 59985
Summary: stage2/3 compare error on lto-streamer-in.o
Product: gcc
Version: 4.9.0
Status: UNCONFIRMED
Severity: normal
Priority: P3
Component: bootstrap
Assignee: unassigned at gcc dot gnu.org
Reporter: bernd.edlinger at hotmail dot de
I try to boot strap this on arm-linux-gnueabihf:
../gcc-4.9-20140126/configure --prefix=/home/ed/gnu/arm-linux-gnueabihf
--enable-languages=c,c++,objc,obj-c++,fortran,ada,go --with-arch=armv7-a
--with-tune=cortex-a9 --with-fpu=vfpv3-d16 --with-float=hard
and get a stage2/3 compare error constantly at lto-streamer-in.o
this is reproducible with gcc snapshot gcc-4.9-20140126
as well as gcc-4.9-20140112.
--- stage2.dump 2014-01-29 14:38:32.291550833 +0000
+++ stage3.dump 2014-01-29 14:38:53.595551113 +0000
@@ -1093,19 +1093,19 @@
1084: e58d3010 str r3, [sp, #16]
1088: e2082001 and r2, r8, #1
108c: e3a03000 mov r3, #0
- 1090: e1a08000 mov r8, r0
+ 1090: e3a06003 mov r6, #3
1094: e1cd20f8 strd r2, [sp, #8]
- 1098: e1a0e001 mov lr, r1
+ 1098: e3a0c004 mov ip, #4
109c: e59d3010 ldr r3, [sp, #16]
- 10a0: e3a06003 mov r6, #3
- 10a4: e3a0c004 mov ip, #4
+ 10a0: e1a08000 mov r8, r0
+ 10a4: e1a0e001 mov lr, r1
10a8: e1833f01 orr r3, r3, r1, lsl #30
10ac: e58d3010 str r3, [sp, #16]
10b0: e1a03121 lsr r3, r1, #2
10b4: e58d3014 str r3, [sp, #20]
- 10b8: e3a03000 mov r3, #0
- 10bc: e1cd01d0 ldrd r0, [sp, #16]
- 10c0: e2002001 and r2, r0, #1
+ 10b8: e1cd21d0 ldrd r2, [sp, #16]
+ 10bc: e3a03000 mov r3, #0
+ 10c0: e2022001 and r2, r2, #1
10c4: e1cd21f0 strd r2, [sp, #16]
10c8: ea000009 b 10f4
<_Z18lto_input_locationP9bitpack_dP7data_in+0x230>
10cc: e5940010 ldr r0, [r4, #16]
This seems to happen because stage2 uses -gtoggle and stage3 does not.
I see the first difference in lto-streamer-in.c.234r.sched2:
stage2:
(insn 484 475 485 17 (set (reg:SI 2 r2 [orig:118 D.60233 ] [118])
(and:SI (reg:SI 8 r8 [orig:256 valD.60190 ] [256])
(const_int 1 [0x1])))
../../gcc-4.9-20140126/gcc/data-streamer.h:172 80 {*arm_andsi3_insn}
(expr_list:REG_DEAD (reg:SI 8 r8 [orig:256 valD.60190 ] [256])
(nil)))
(insn:TI 485 484 348 17 (set (reg:SI 3 r3 [ D.60233+4 ])
(const_int 0 [0])) ../../gcc-4.9-20140126/gcc/data-streamer.h:172 663
{*arm_movsi_vfp}
(nil))
(insn 348 485 461 17 (set (reg:SI 8 r8 [orig:270 D.60233 ] [270])
(reg:SI 0 r0 [orig:140 valD.60184 ] [140]))
../../gcc-4.9-20140126/gcc/data-streamer.h:172 663 {*arm_movsi_vfp}
(expr_list:REG_DEAD (reg:SI 0 r0 [orig:140 valD.60184 ] [140])
(nil)))
(insn:TI 461 348 349 17 (set (mem/c:DI (plus:SI (reg/f:SI 13 sp)
(const_int 8 [0x8])) [180 %sfpD.60006+-48 S8 A64])
(reg:DI 2 r2 [orig:118 D.60233 ] [118]))
../../gcc-4.9-20140126/gcc/data-streamer.h:172 665 {*movdi_vfp}
(expr_list:REG_DEAD (reg:DI 2 r2 [orig:118 D.60233 ] [118])
(nil)))
stage3:
(insn 622 613 623 17 (set (reg:SI 2 r2 [orig:118 D.60549 ] [118])
(and:SI (reg:SI 8 r8 [orig:256 valD.60503 ] [256])
(const_int 1 [0x1])))
../../gcc-4.9-20140126/gcc/data-streamer.h:172 80 {*arm_andsi3_insn}
(expr_list:REG_DEAD (reg:SI 8 r8 [orig:256 valD.60503 ] [256])
(nil)))
(insn:TI 623 622 438 17 (set (reg:SI 3 r3 [ D.60549+4 ])
(const_int 0 [0])) ../../gcc-4.9-20140126/gcc/data-streamer.h:172 663
{*arm_movsi_vfp}
(nil))
(insn 438 623 598 17 (set (reg/v:SI 6 r6 [orig:113 posD.60516 ] [113])
(const_int 3 [0x3])) 663 {*arm_movsi_vfp}
(nil))
(insn:TI 598 438 428 17 (set (mem/c:DI (plus:SI (reg/f:SI 13 sp)
(const_int 8 [0x8])) [180 %sfpD.60308+-48 S8 A64])
(reg:DI 2 r2 [orig:118 D.60549 ] [118]))
../../gcc-4.9-20140126/gcc/data-streamer.h:172 665 {*movdi_vfp}
(expr_list:REG_DEAD (reg:DI 2 r2 [orig:118 D.60549 ] [118])
(nil)))
