[Bug rtl-optimization/56885] [4.8/4.9 Regression] ICE: in assign_by_spills, at lra-assigns.c:1268 with -O -fschedule-insns -fselective-scheduling

[ysrumyan at gmail dot com]

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=56885



--- Comment #5 from Yuri Rumyantsev <ysrumyan at gmail dot com> 2013-04-09 
13:33:53 UTC ---

I did simple investigation and found out that

1. Test is compiled successfully without selective scheduling, i.e. with

'-fschedule-insns' only.

2. The problem is that selective scheduler moves function argument (off) uo

through bunch of instructions correspondent to __builtin_memset() ignoring

dependency creating by ix86_dependencies_evaluation_hook() ( i tried to add

output dependency instead of anti dependency between them but it also did not

help). More precisely, we have the following sequence of insns:



(insn 30 29 31 5 (parallel [

            (set (reg:DI 77)

                (const_int 0 [0]))

            (set (reg/f:DI 75 [ D.1742 ])

                (plus:DI (reg/f:DI 74 [ D.1742 ])

                    (reg:DI 77)))

            (set (mem:BLK (reg/f:DI 74 [ D.1742 ]) [0 MEM[(void *)_17]+0 S15

A8])

                (const_int 0 [0]))

            (use (reg:QI 78))

            (use (reg:DI 77))

        ]) t.c:16 909 {*rep_stosqi}

     (expr_list:REG_DEAD (reg/f:DI 74 [ D.1742 ])

        (expr_list:REG_UNUSED (reg:DI 77)

            (expr_list:REG_UNUSED (reg/f:DI 75 [ D.1742 ])

                (nil)))))

(insn 31 30 32 5 (set (reg:SI 5 di)

        (subreg:SI (reg:DI 69 [ ivtmp.3 ]) 0)) t.c:17 85 {*movsi_internal}

     (nil))

(call_insn 32 31 33 5 (call (mem:QI (symbol_ref:DI ("bar") [flags 0x41] 

<function_decl 0x7f66061e4900 bar>) [0 bar S1 A8])

        (const_int 0 [0])) t.c:17 646 {*call}

     (expr_list:REG_DEAD (reg:SI 5 di)

        (nil))

    (expr_list:REG_BR_PRED (use (reg:SI 5 di))

        (nil)))



and there exist anti or output dependency between 30 and 31 insns created by

ix86-hook which is ignored by selective scheduler:



Moving [((31;di=r69#0;)type:set;count:2;)prio:3;orig_bb:5;] through 30:

unchanged (as RHS)



So I assume that selective scheduler needs to be tuned to be invoked before

Register Allocation phase on x86.