http://gcc.gnu.org/bugzilla/show_bug.cgi?id=53513
--- Comment #1 from Oleg Endo <olegendo at gcc dot gnu.org> 2013-03-10 19:53:56 UTC --- Some related notes: According to the public documentation, the 'fschg' insn is only valid when FPSCR.PR = 0 on all FPU enabled cores (SH2A, SH4, SH4A). On SH4 and SH4A the 'frchg' insn is only valid when FPSCR.PR = 0. The setting FPSCR.PR = 1, FPSCR.SZ = 1 is only valid for SH4A and SH2A, but not SH4.
