http://gcc.gnu.org/bugzilla/show_bug.cgi?id=55298
Bug #: 55298
Summary: [SH] Add support to disable FPU usage for individual
functions
Classification: Unclassified
Product: gcc
Version: 4.8.0
Status: UNCONFIRMED
Severity: enhancement
Priority: P3
Component: target
AssignedTo: unassig...@gcc.gnu.org
ReportedBy: olege...@gcc.gnu.org
Target: sh*-*-*
On SH3* and SH4* targets, 'fast interrupt handlers' (non-reentrant ISRs) can be
implemented by specifying the 'interrupt_handler' and 'nosave_low_regs'
function attributes. If such an ISR invokes another function the compiler
currently generates push/pop insns for all call clobbered FP registers. This
could be avoided by specifying another function attribute ('nofpu') to turn off
hardware FPU usage for a particular function. A 'nofpu' ISR that invokes only
'nofpu' functions then does not need to push/pop any FP registers.
Some ABI compatibility issues I can think of at the moment are:
When a 'nofpu' function invokes a normal function (that could use the FPU or
takes any args in FP regs) the best thing is probably to issue a compile time
error.
When a normal function invokes a 'nofpu' function that does not take any FP
args (in registers) there is no problem.
When a normal function invokes a 'nofpu' function that takes FP args in GP regs
the call must use the 'nofpu' ABI.
Alternatively, the compiler could generate two versions of 'nofpu' functions.
One version that follows the 'nofpu' ABI and a normal version. Normal
functions that invoke 'nofpu' functions could then switch to a call to the
normal variant of the 'nofpu' function. The duplicated code would then be
eliminated by the linker.
Note: Currently the only way to disable HW FPU usage is to specify e.g.
'-m4-nofpu', which only works for whole translation units. Also, due to the
ABI differences invoking functions in translation units that were compiled with
'-m4-nofpu' from translation units compiled with '-m4' is not going to work.
