http://gcc.gnu.org/bugzilla/show_bug.cgi?id=54760
Oleg Endo <olegendo at gcc dot gnu.org> changed:
What |Removed |Added
----------------------------------------------------------------------------
Status|RESOLVED |REOPENED
CC| |kkojima at gcc dot gnu.org
Resolution|FIXED |
--- Comment #5 from Oleg Endo <olegendo at gcc dot gnu.org> 2012-10-11 20:29:12
UTC ---
It seems that the proposed target independent thread pointer stuff made it into
mainline. I guess the SH specific built-ins can be removed now. I will check
it out.
Another thing that I'm not sure about is whether 'ldc rn,gbr' and 'stc
gbr,rn' instructions can go in the delay slot, or whether they will cause a
slot illegal exception. Currently this
void* test (void)
{
return __builtin_thread_pointer ();
}
will result in
rts
stc gbr,r0
I've looked in the source of the GDB sim and it seems that the sim will not
detect this as a slot illegal instruction. However, the sim will also not
detect 'stc sgr,rn' as a slot illegal instruction, but in my older
interrupt/exception code I was doing:
stc sgr,r15
rte
nop
because otherwise it would cause trouble.
The HW manuals unfortunately don't mention any details. Basically all of them
say: stc, stc.l, ldc, ldc.l instructions might cause a slot illegal exception.
But it doesn't say which register combinations are slot illegal and which are
legal.
Kaz, do you happen to know something regarding this matter?
