http://gcc.gnu.org/bugzilla/show_bug.cgi?id=54369
--- Comment #7 from rdsandiford at googlemail dot com <rdsandiford at googlemail dot com> 2012-09-01 08:16:23 UTC --- "ebotcazou at gcc dot gnu.org" <gcc-bugzi...@gcc.gnu.org> writes: >> Are you going to check this in on the mainline? > > Not without Richard's approval, so I've CCed him now. Looks good, thanks. Please go ahead. Just out of interest, you said: > The root cause of the problem is that MIPS runs its own version of the dbr > pass > and doesn't make sure that barriers are correctly placed for it, unlike other > targets like SPARC. But how does SPARC do it? sparc_reorg starts: /* The only erratum we handle for now is that of the AT697F processor. */ if (!sparc_fix_at697f) return; /* We need to have the (essentially) final form of the insn stream in order to properly detect the various hazards. Run delay slot scheduling. */ if (optimize > 0 && flag_delayed_branch) dbr_schedule (get_insns ()); without any explicit call to cleanup_barriers (which like you say usually runs after machine_reorg but before delay_slots).