http://gcc.gnu.org/bugzilla/show_bug.cgi?id=53652
--- Comment #2 from Jakub Jelinek <jakub at gcc dot gnu.org> 2012-06-14
10:23:31 UTC ---
Such a def_insn_and_split isn't going to work well, because the hw supported
alternative (xor with all ones vector) needs the vector constant loaded into
memory, which is much preferrable to be done before loop, and nothing post
combine is going to move it before the loop again.
The combiner can already look at the REG_EQUAL note:
(insn 25 21 27 3 (set (reg:V4DI 90 [ vect_var_.18 ])
(xor:V4DI (mem:V4DI (plus:DI (reg:DI 78 [ ivtmp.28 ])
(symbol_ref:DI ("c") <var_decl 0x7f09fb364280 c>)) [2
MEM[symbol: c, index: ivtmp.28_16, offset: 0B]+0 S32 A256])
(reg:V4DI 94))) v2.c:10 1587 {*xorv4di3}
(expr_list:REG_EQUAL (not:V4DI (mem:V4DI (plus:DI (symbol_ref:DI ("c")
<var_decl 0x7f09fb364280 c>)
(reg:DI 78 [ ivtmp.28 ])) [2 MEM[symbol: c, index:
ivtmp.28_16, offset: 0B]+0 S32 A256]))
(nil)))
(insn 27 25 28 3 (set (reg:V4DI 93 [ vect_var_.19 ])
(and:V4DI (reg:V4DI 90 [ vect_var_.18 ])
(mem:V4DI (plus:DI (reg:DI 78 [ ivtmp.28 ])
(symbol_ref:DI ("b") <var_decl 0x7f09fb3641e0 b>)) [2
MEM[symbol: b, index: ivtmp.28_16, offset: 0B]+0 S32 A256]))) v2.c:10 1585
{*andv4di3}
(expr_list:REG_DEAD (reg:V4DI 90 [ vect_var_.18 ])
(nil)))
but doesn't use that. The additional complication here is that both the XOR
(and REG_EQUAL not note) and the other AND operand are both MEMs, while andn on
x86_64/i?86 only supports one of the operands as MEM. The combiner would then
need to split that into a load followed by andn (in place of the 3 insns (one
load before the loop, xor and and).
