[Bug target/53133] XOR AL,AL to zero lower 8 bits of EAX/RAX causes partial register stall (Intel Core 2)

[ubizjak at gmail dot com]

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=53133

--- Comment #2 from Uros Bizjak <ubizjak at gmail dot com> 2012-04-30 13:19:56 
UTC ---
This is due to following splitter in i386.md:

(define_split
  [(set (match_operand 0 "ext_register_operand")
    (and (match_dup 0)
         (const_int -256)))
   (clobber (reg:CC FLAGS_REG))]
  "(!TARGET_PARTIAL_REG_STALL || optimize_function_for_size_p (cfun))
   && reload_completed"
  [(set (strict_low_part (match_dup 1)) (const_int 0))]
  "operands[1] = gen_lowpart (QImode, operands[0]);")

However, Core architecture is not listed under X86_TUNE_PARTIAL_REG_STALL,
although my documentation says that following latency should be added due to
partial reg stall:

PPro, P2, P3  : 5
Core          : 1-5
Core2, Corei7 : 1-6

H.J., should we consider these processors as affected by partial reg stall?