[Bug middle-end/52306] ICE in CSE

[aoliva at gcc dot gnu.org]

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=52306

--- Comment #1 from Alexandre Oliva <aoliva at gcc dot gnu.org> 2012-03-25 
12:00:34 UTC ---
The bug, duplicated by compiling attachment 26150, from bug 43437 comment 16,
with a cross-compiler to m68k-elf with -O -c, exposes a reload problem.  Before
reload, we have this insn:

(insn 288 287 290 40 (set (reg/f:SI 124 [ D.1788 ])
        (mem/f:SI (post_inc:SI (reg:SI 145 [ ivtmp.76 ])) [5 MEM[base:
D.1889_285, offset: 0B]+0 S4 A16])) pr52306.c:278 37 {*movsi_m68k2}
     (expr_list:REG_INC (reg:SI 145 [ ivtmp.76 ])
        (nil)))

reload turns this into:

(insn 639 287 640 40 (set (reg:SI 9 %a1)
        (mem/c:SI (plus:SI (reg/f:SI 14 %a6)
                (const_int -44 [0xffffffffffffffd4])) [13 %sfp+-44 S4 A16]))
pr5
2306.c:278 36 {*movsi_m68k}
     (nil))

(insn 640 639 288 40 (set (mem/c:SI (plus:SI (reg/f:SI 14 %a6)
                (const_int -44 [0xffffffffffffffd4])) [13 %sfp+-44 S4 A16])
        (plus:SI (mem/c:SI (plus:SI (reg/f:SI 14 %a6)
                    (const_int -44 [0xffffffffffffffd4])) [13 %sfp+-44 S4 A16])
            (const_int 4 [0x4]))) pr52306.c:278 132 {*addsi3_internal}
     (nil))

(insn 288 640 290 40 (set (reg:SI 9 %a1)
        (mem/f:SI (post_inc:SI (reg:SI 9 %a1)) [5 MEM[base: D.1889_285, offset:
0B]+0 S4 A16])) pr52306.c:278 37 {*movsi_m68k2}
     (expr_list:REG_INC (reg:SI 9 %a1)
        (nil)))

reload correctly performs the post_inc in a separate insn, but it fails to
remove the post_inc from the MEM that had it, so we end up with two concurrent
modifications of the same register, which is not well-formed RTX.