http://gcc.gnu.org/bugzilla/show_bug.cgi?id=48203
--- Comment #11 from Ramana Radhakrishnan <ramana at gcc dot gnu.org>
2011-03-19 22:14:50 UTC ---
(In reply to comment #10)
> (In reply to comment #9)
> > Can you try with -mcpu=cortex-a9 -mfpu=vfpv3-d16 -mfloat-abi=softfp -mthumb
> > ?
> > It fails in that case . #c1 has the configuration options that I used.
>
> Can't reproduce, neither with the above options, nor with a fresh cross
> configured the way you mentioned in #c0.
I see the ICE with -mcpu=cortex-a9 -mfpu=vfpv3-d16 -mfloat-abi=softfp -marm .
It appears as though when I did a quick rebuild of the tools to verify your
patch I missed the --with-mode=thumb. Sorry about the confusion.
I've dug into this a bit further and it appears as though the ICE at
21979 gcc_assert (prev
21980 && (CALL_P (prev)
21981 || (NONJUMP_INSN_P (prev)
21982 && GET_CODE (PATTERN (prev)) == SEQUENCE
21983 && CALL_P (XVECEXP (PATTERN (prev), 0, 0)))));
Looking at the backtrace it appears as though the assertion failure is because
we don't see the call before the note. Looking at the dumps the ARM backend
ends up generating the minipools to interleave the constant pools within the
function because of range issues and thus end up breaking the assertion. The
work around is then to emit the barriers and the minipools after the notes
rather than just after the "call insn".
2265 call [`obstack_free'] argc:0
REG_DEAD: r1:SI
REG_DEAD: r0:SI
4874 pc=L4876
i4875: barrier
L4877:
4878 unspec/v{0;}
L4879:
4880 unspec/v{1.399999999999999911182158029987476766109466552734375e+0;}
4881 unspec/v{`swap_endianness_p';}
4882 unspec/v{const(`*.LANCHOR1'+0x7d0);}
4883 unspec/v{const(`*.LANCHOR1'+0x2c);}
4884 unspec/v{const(`*.LANCHOR1'+0x7bc);}
4885 unspec/v{const(`*.LANCHOR1'+0x7a8);}
4886 unspec/v{const(`*.LANCHOR1'+0x70c);}
4887 unspec/v{const(`*.LANCHOR1'+0x218);}
4888 unspec/v{0;}
i4889: barrier
L4876:
4011 NOTE_INSN_CALL_ARG_LOCATION
4012 NOTE_INSN_VAR_LOCATION
4013 NOTE_INSN_VAR_LOCATION
