http://gcc.gnu.org/bugzilla/show_bug.cgi?id=47454
Summary: registers are not allocated according to its preferred
order
Product: gcc
Version: 4.6.0
Status: UNCONFIRMED
Severity: normal
Priority: P3
Component: rtl-optimization
AssignedTo: [email protected]
ReportedBy: [email protected]
Target: arm-linux-androideabi
Created attachment 23115
--> http://gcc.gnu.org/bugzilla/attachment.cgi?id=23115
testcase
The attached test case is extracted from zlib, when compiled by gcc4.6 with
options -march=armv7-a -mthumb -Os, I got the following code
push {r4, r5, r6, r7, r8, lr}
mov r6, r0
mov r4, r1
cmp r0, #0
beq .L2
ldr r5, [r0, #0]
cmp r5, #0
beq .L2
cmp r1, #0
bge .L3
negs r4, r1
movs r7, #0
b .L4
.L3:
asrs r7, r1, #4
adds r7, r7, #1
cmp r1, #47
it le
andle r4, r1, #15
.L4:
adds r3, r4, #0
sub r8, r4, #8
it ne
movne r3, #1
cmp r8, #7
ite ls
movls r8, #0
andhi r8, r3, #1
cmp r8, #0
bne .L2
ldr r1, [r5, #8]
cbz r1, .L5
ldr r3, [r5, #4]
cmp r3, r4
beq .L5
ldr r3, [r6, #4]
ldr r0, [r6, #8]
blx r3
str r8, [r5, #8]
.L5:
str r7, [r5, #0]
mov r0, r6
str r4, [r5, #4]
pop {r4, r5, r6, r7, r8, lr}
b inflateReset
.L2:
mvn r0, #1
pop {r4, r5, r6, r7, r8, pc}
Note that register r8 is used many times, but register r2 is never used. In
thumb2 r8 is high register, its usage will cause 32bit instructions. If we
replace r8 with r2, a lot of code size will be reduced in this case.
In arm.h REG_ALLOC_ORDER is defined as
3, 2, 1, 0, 12, 14, 4, 5, 6, 7, 8, 10, 9, 11, 13, 15 ...
We can see that r2 should be used before r8, but the result is not.
