------- Comment #29 from ian dot bolton at arm dot com 2010-07-09 17:02 -------
(In reply to comment #7)
> When I read the RTL dumps correctly, gcc tries to assign SP to wCGR0.
SP is actually the destination here, not the source.
> This can be done by the
>
> tmrc sp, wCGR0
>
> assembly instruction which will be issued by alternative 6 in
>
>
> --- iwmmxt.md ---
> (define_insn "*iwmmxt_movsi_insn"
> [(set (match_operand:SI 0 "nonimmediate_operand" "=rk,r,r,rk,
> m,z,r,?z,Uy,z")
> (match_operand:SI 1 "general_operand" "rk, I,K,mi,rk,r,z,Uy,z,
> z"))]
> ...
> case 6: return \"tmrc\\t%0, %1\";
>
>
> The corresponding constraints pair is ['r', 'z'] and it is matched by
> [sp, wcgr0] afais. What could be the reason for the ICE?
>
As existing replies already point out, the ICE is being caused by the fact that
SP does not meet the "r" constraint (you need "k" to specify SP). However, if
the constraint were valid, and the assignment to SP was allowed to occur, you
would essentially be using SP as a general purpose register when it is special
and should not be used this way.
Based on my limited (so far) understanding of the ARM port of GCC, I think the
fault lies either with the predicate (nonimmediate_operand), which is allowing
SP to be the dest, or the code that created the iwmmxt_movsi_insn with SP as
its dest. There was a time (before Thumb-2, I think) when SP could be used as
a general purpose register, so maybe some IWMMXT-related code needs updating to
reflect this.
--
ian dot bolton at arm dot com changed:
What |Removed |Added
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CC| |ian dot bolton at arm dot
| |com
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=40836
