------- Comment #3 from ubizjak at gmail dot com 2010-04-19 13:34 -------
>From sse.md:
;; ??? In theory we can match memory for the MMX alternative, but allowing
;; nonimmediate_operand for operand 2 and *not* allowing memory for the SSE
;; alternatives pretty much forces the MMX alternative to be chosen.
(define_insn "*vec_concatv2si_sse2"
[(set (match_operand:V2SI 0 "register_operand" "=x,x ,*y,*y")
(vec_concat:V2SI
(match_operand:SI 1 "nonimmediate_operand" " 0,rm, 0,rm")
(match_operand:SI 2 "reg_or_0_operand" " x,C ,*y, C")))]
"TARGET_SSE2"
Since this insn is part of expand_vector_init sequences, changing RA
preferences will result in the usage of MMX registers in the construction of
i.e. V4SI vector. When MMX registers are touched, x87 register stack switches
to MMX mode, so gcc will go really far to avoid touching MMX registers. The
problem you show is the result of this, and changing the delicate balance of
MMX register allocation preferences will just result in Really Annoying
Problems elsewhere.
Just stay away of MMX registers as much as possible.
--
ubizjak at gmail dot com changed:
What |Removed |Added
----------------------------------------------------------------------------
Status|NEW |RESOLVED
Resolution| |WONTFIX
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=43743
