------- Comment #7 from ramana at gcc dot gnu dot org 2010-03-21 09:23 ------- (In reply to comment #5)
> The proper solution seems to be extremely simple to me and it should do > exactly > the same what an application programmer would do to workaround the bug. Just > when initially parsing clobber list do a simple text substitution "q0" -> > "d0", > "d1". Same for all the other "q" registers. > Maybe I wasn't clear enough. If you've written to s3 and used q0 some place in your program then you want to indicate that q0 has been clobbered. IIUC the way the Neon registers are represented in GCC is by having the same register "number" for s0, d0 and q0 - thus the clobber list generated for your inline asm statement at expand time is essentialy clobber ( reg:QI 68) or whatever be the register number for s0, d0 and q0. Thus at the time the register allocator comes along you've lost all information regarding the mode in which the register was used and it would think that just s0 was being clobbered. Thus the clean solution to this IMO is to have some way of representing a proper mode for each of the register numbers and then making the register allocator / other optimizers honour it. In theory it should work but in practice I'm not sure if that's the correct thing to do in stage4. This isn't a problem in standard C code because the RTL for accessing those variables would have the Mode in which the registers were being accessed and thus any overlapping can be detected. Hope that makes things clearer. Ramana -- http://gcc.gnu.org/bugzilla/show_bug.cgi?id=43440
