------- Comment #8 from astrange at ithinksw dot com 2008-12-05 20:08 -------
With some recent changes IRA makes better decisions now but they don't survive
reload.
Using
> /gcc -O3 -fomit-frame-pointer -fno-pic -fdump-rtl-ira -S cabac-ret.i
I get about the same asm and this in the IRA dump:
**** Allocnos coloring:
Loop 0 (parent -1, header bb0, depth 0)
bbs: 2
all: 0r64 1r58 2r62 3r59 4r60 5r63
modified regnos: 58 59 60 62 63 64
border:
Pressure: GENERAL_REGS=6
Reg 58 of GENERAL_REGS has 2 regs less
Reg 62 of GENERAL_REGS has 2 regs less
Reg 59 of GENERAL_REGS has 2 regs less
Reg 60 of GENERAL_REGS has 2 regs less
Reg 63 of GENERAL_REGS has 2 regs less
Pushing a0(r64,l0)
Pushing a3(r59,l0)(potential spill: pri=2857, cost=20000)
Pushing a1(r58,l0)
Pushing a5(r63,l0)
Pushing a2(r62,l0)
Pushing a4(r60,l0)
Popping a4(r60,l0) -- assign reg 3
Popping a2(r62,l0) -- assign reg 4
Popping a5(r63,l0) -- assign reg 0 <- "r"(state)
Popping a1(r58,l0) -- assign reg 0 <- "=&r"(bit)
Popping a3(r59,l0) -- assign reg 5
Popping a0(r64,l0) -- assign reg 0 <- returned bit&1
a1 and a5 should be conflicting, since a1 is an earlyclobber output and can't
share a register with any of the inputs. reload fixes this by moving it to a
worse register.
--
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=36539
