------- Comment #17 from sergstesh at yahoo dot com 2006-11-19 02:20 ------- Regarding
" > Is it that gcc-4.1.1 falsely aligns the memory location in question ? Well it can be 8byte aligned and accidently also 16byte aligned (which does happen every once in a while). " The original report shows: " &inp_array_1[1]=80498e4 checkpoint 3 Segmentation fault " , i.e. the failing address is not 8 bytes aligned, it's 4 bytes aligned. Regarding " > I am specifically interested in the "or your program will segfault" part ? This is call debugging your program. Also you really should read web pages about SSE programming because it seems like you don't understand how to use. " I did read documentation on the issue, beginning from gcc manual. You correctly point out that by default aligned loads are used, which are faster, and Intel documentation says that misaligned address in such a case causes general protection fault. Which can be dealt with by kernel. The point is that I do not recall in the gcc manual mentioning of the default aligned load. Adding one sentence (if it's not yet there) would make life of both end users and developers easier - the developers will have to deal with smaller amount of bug reports like this one. Regarding " Also using mode with vector mode is deprecated and you should be using vector_size instead. " - sure, just gcc-3.4.6 doesn't understand this. I do not remember how the gcc version macro is called, so I used the code which was compatible with both gcc-3.4.6 and gcc-4.1.1, though it produces warning on gcc-4.1.1. -- http://gcc.gnu.org/bugzilla/show_bug.cgi?id=29818
