------- Comment #4 from eplondke at gmail dot com  2006-10-02 19:16 -------
(In reply to comment #3)
> Actually this case should not be using post modify at all except how many bits
> does ARM have to use for an offset? I thought 16bits which means you don't 
> need
> that at all and GCC should generate it without an increment.  Oh and this is a
> RTL opt issue.
> 

ARM normal arithmetic operands support an 8-bit integer rotated right by an
even
number of bits (0-30).  If you rotate at all some microarchitectures may cause 
stalls (Xscale maybe?)...

Load and Store word (and unsigned byte) have a +/- 12-bit offset.
Load and store other single values has a +/- 8-bit offset.
Load and store multiple may have no offset.

That's for ARM.  For THUMB, you get + 5 bits.

Both ARM and THUMB mode have postincrement modes.  ARM gets a decent
postmodify.  For THUMB you use the Load Multiple Increment After instruction
with a single
regster specified.

Looks like CSE1 is the first time that 

(set (reg) (mem (reg))) gets converted to
(set (reg) (mem (plus (reg) (4))))

I have noticed a propensity for postmodify to not be used in several targets 
comparing GCC 4.X to GCC 3.X.


-- 


http://gcc.gnu.org/bugzilla/show_bug.cgi?id=29294

Reply via email to