Currently, the only check for CLASS_LIKELY_SPILLED registers is for instuctions
at the end of a basic block; this is insufficient, since a set/use pair of
a CLASS_LIKELY_SPILLED register can be in the middle of the block. When
the scheduler inserts an instruction between into this pair which needs
a reload with the same class as the likely spilled register, a reload failure
is inevitable for calsses of size 1.
--
Summary: The scheduler extends the lifetime of
CLASS_LIKELY_SPILLED registers
Product: gcc
Version: 4.2.0
Status: UNCONFIRMED
Keywords: ice-on-valid-code
Severity: normal
Priority: P3
Component: rtl-optimization
AssignedTo: unassigned at gcc dot gnu dot org
ReportedBy: amylaar at gcc dot gnu dot org
GCC target triplet: sh-elf (modified)
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=28618
