GCC provides the programmer the ability to use SIMD instructions by primitives.
These are defined in header files. Unfortunately, GCC follows Intel compiler
conventions. But these conventions, dictated by Intel interests, not always
reflect correctly the reality, specially of AMD processors.
According to these conventions, there are four levels of SIMD instructions:
Pentium MMX: MMX instructions.
Pentium III and higher: MMX + SSE single precission floating point
instructions.
Pentium IV and higher: MMX + SSE single precission + SSE2 integer and double
precission
Newer Pentium IV: MMX + SSE + SSE2 + SSE3
This model does not reflect correctly AMD Atlon processors, that support SSE
integer SIMD instructions but do not support SSE2 double precission
instructions.
While it is natural that Intel compiler is aligned with the company's
interests, it is not acceptable that a vendor neutral free software project
follows them.
Thus it is necessary to add a new level that includes integer SSE instructions
without including double precission SIMD instructions.
What I request is:
- A flag to support Athlon SSE set of instructions. As it is in the middle of
SSE and SSE2 it might be called SSE1.5, with the option -msse1.5.
- A header file that defines SSE integer instructions without define SSE double
precission instructions. Since GCC already ships xmmintrin.h, a new header file
immintrin.h could be added. This second part is trivial to do and in my opinion
should be included in GCC 4.1.1.
Both changes are backward compatible.
--
Summary: SSE instruction selection wrong for Athlon processors.
Product: gcc
Version: 4.1.0
Status: UNCONFIRMED
Severity: enhancement
Priority: P3
Component: c
AssignedTo: unassigned at gcc dot gnu dot org
ReportedBy: ramsgar-gccbug at yahoo dot com
GCC target triplet: i586-anyone-linux
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=27562
