[Bug target/26636] use of r1-r3 across __sdivsi3_4 call

[rmansfield at qnx dot com]

------- Comment #2 from rmansfield at qnx dot com  2006-03-15 16:20 -------
I looked at the RTL generated to find what pass R1 was first introduced and it
was greg. It appears (I'm not certain since I'm still learning to read RTL) the
that no clobber happens for the divsi3_i4 insn.

Looking at sh.md, R1-R3 are clobbered in the define_expand for divsi3

(define_expand "divsi3"
  [(set (match_dup 3) (symbol_ref:SI "__sdivsi3"))
   (set (reg:SI R4_REG) (match_operand:SI 1 "general_operand" ""))
   (set (reg:SI R5_REG) (match_operand:SI 2 "general_operand" ""))
   (parallel [(set (match_operand:SI 0 "register_operand" "")
         (div:SI (reg:SI R4_REG)
            (reg:SI R5_REG)))
         (clobber (reg:SI T_REG))
         (clobber (reg:SI PR_REG))
         (clobber (reg:SI R1_REG))
         (clobber (reg:SI R2_REG))
         (clobber (reg:SI R3_REG))
         (use (match_dup 3))])]

{
  rtx first, last;

  operands[3] = gen_reg_rtx (Pmode);
 ...
  last = gen_divsi3_i4 (operands[0], operands[3]);


The define_insn for divsi3_i4 does not have the R1-R3 clobbers as they did in
2.95.3


 (define_insn "divsi3_i4"
   [(set (match_operand:SI 0 "register_operand" "=y")
    (div:SI (reg:SI R4_REG) (reg:SI R5_REG)))
    (clobber (reg:SI PR_REG))
    (clobber (reg:DF DR0_REG))
    (clobber (reg:DF DR2_REG))
    (use (reg:PSI FPSCR_REG))
    (use (match_operand:SI 1 "arith_reg_operand" "r"))]
   "TARGET_SH4 && ! TARGET_FPU_SINGLE"
   "jsr   @%1%#"
   [(set_attr "type" "sfunc")
    (set_attr "fp_mode" "double")
    (set_attr "needs_delay_slot" "yes")])

in 2.95.3:

(define_insn "divsi3_i4"
  [(set (match_operand:SI 0 "register_operand" "=y")
   (div:SI (reg:SI 4) (reg:SI 5)))
   (clobber (reg:SI 18))
   (clobber (reg:SI 17))
   (clobber (reg:DF 24))
   (clobber (reg:DF 26))
   (clobber (reg:SI 0))
   (clobber (reg:SI 1))
   (clobber (reg:SI 2))


How is the clobber list for define_expand insn expected to work? Should it
clobber for all emitted rtl insns? 

Adding:

         (clobber (reg:SI R1_REG))
         (clobber (reg:SI R2_REG))
         (clobber (reg:SI R3_REG))

to the "divsi3_i4" insn gets around the problem, but is that the proper
solution?


-- 


http://gcc.gnu.org/bugzilla/show_bug.cgi?id=26636