On Mon, 09 Mar 2026 14:37:20 +0800, yuanjie yang wrote:
> During DPU runtime suspend, calling dev_pm_opp_set_rate(dev, 0) drops
> the MMCX rail to MIN_SVS while the core clock frequency remains at its
> original (highest) rate. When runtime resume re-enables the clock, this
> may result in a mismatch between the rail voltage and the clock rate.
>
> For example, in the DPU bind path, the sequence could be:
> cpu0: dev_sync_state -> rpmhpd_sync_state
> cpu1: dpu_kms_hw_init
> timeline 0 ------------------------------------------------> t
>
> [...]
Applied to msm-next, thanks!
[1/1] drm/msm/dpu: fix mismatch between power and frequency
https://gitlab.freedesktop.org/lumag/msm/-/commit/bc1dccc518cc
Best regards,
--
With best wishes
Dmitry
