[PATCH v4 12/19] drm/msm/dpu: Add handling of LM_6 and LM_7 bits in pending flush mask

[Krzysztof Kozlowski]

MDSS/MDP v12 comes with new bits in flush registers (e.g.
MDP_CTL_0_FLUSH) for Layer Mixer 6 and 7.

Reviewed-by: Dmitry Baryshkov <dmitry.barysh...@linaro.org>
Reviewed-by: Jessica Zhang <quic_jessz...@quicinc.com>
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlow...@linaro.org>
---
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
index 
2ce59ba50ffa0d14eaa07e993fadf0f218390ef1..3e5e1e09e9d00ade74371489b2b4e50e648e2d16
 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
@@ -261,6 +261,12 @@ static void dpu_hw_ctl_update_pending_flush_mixer(struct 
dpu_hw_ctl *ctx,
        case LM_5:
                ctx->pending_flush_mask |= BIT(20);
                break;
+       case LM_6:
+               ctx->pending_flush_mask |= BIT(21);
+               break;
+       case LM_7:
+               ctx->pending_flush_mask |= BIT(27);
+               break;
        default:
                break;
        }

-- 
2.43.0