Currently, SSPPs are assigned to a maximum of two pipes. However,
quad-pipe usage scenarios require four pipes and involve configuring
two stages. In quad-pipe case, the first two pipes share a set of
mixer configurations and enable multi-rect mode when certain
conditions are met. The same applies to the subsequent two pipes.
Assign SSPPs to the pipes in each stage using a unified method and
to loop the stages accordingly.
Signed-off-by: Jun Nie <jun....@linaro.org>
---
drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 11 ++++++
drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h | 2 +
drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 64 +++++++++++++++++++++----------
3 files changed, 57 insertions(+), 20 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
index
6fbe42e8988edac7e7917ae8de180aefdaf443e9..fa487d625dde5cbd9a83ceb5163c049da45163f7
100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
@@ -1367,6 +1367,17 @@ int dpu_crtc_vblank(struct drm_crtc *crtc, bool en)
return 0;
}
+/**
+ * dpu_crtc_get_num_lm - Get mixer number in this CRTC pipeline
+ * @state: Pointer to drm crtc state object
+ */
+unsigned int dpu_crtc_get_num_lm(const struct drm_crtc_state *state)
+{
+ struct dpu_crtc_state *cstate = to_dpu_crtc_state(state);
+
+ return cstate->num_mixers;
+}
+
#ifdef CONFIG_DEBUG_FS
static int _dpu_debugfs_status_show(struct seq_file *s, void *data)
{
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h
b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h
index
0b148f3ce0d7af80ec4ffcd31d8632a5815b16f1..b14bab2754635953da402d09e11a43b9b4cf4153
100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h
@@ -264,4 +264,6 @@ static inline enum dpu_crtc_client_type
dpu_crtc_get_client_type(
void dpu_crtc_frame_event_cb(struct drm_crtc *crtc, u32 event);
+unsigned int dpu_crtc_get_num_lm(const struct drm_crtc_state *state);
+
#endif /* _DPU_CRTC_H_ */
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
index
1095727d1d9f17407f2b063039bf2efd8733ec70..0245f158881b5c37fffb75d78c75310ba446a0b7
100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
@@ -1115,8 +1115,9 @@ static int dpu_plane_virtual_assign_resources(struct
drm_crtc *crtc,
struct dpu_sw_pipe *r_pipe;
struct dpu_sw_pipe_cfg *pipe_cfg;
struct dpu_sw_pipe_cfg *r_pipe_cfg;
+ struct dpu_plane *pdpu = to_dpu_plane(plane);
const struct msm_format *fmt;
- int i;
+ int i, num_lm, stage_id, num_stages;
if (plane_state->crtc)
crtc_state = drm_atomic_get_new_crtc_state(state,
@@ -1124,11 +1125,6 @@ static int dpu_plane_virtual_assign_resources(struct
drm_crtc *crtc,
pstate = to_dpu_plane_state(plane_state);
- pipe = &pstate->pipe[0];
- r_pipe = &pstate->pipe[1];
- pipe_cfg = &pstate->pipe_cfg[0];
- r_pipe_cfg = &pstate->pipe_cfg[1];
-
for (i = 0; i < PIPES_PER_PLANE; i++)
pstate->pipe[i].sspp = NULL;
@@ -1142,24 +1138,52 @@ static int dpu_plane_virtual_assign_resources(struct
drm_crtc *crtc,
reqs.rot90 = drm_rotation_90_or_270(plane_state->rotation);
- pipe->sspp = dpu_rm_reserve_sspp(&dpu_kms->rm, global_state, crtc,
&reqs);
- if (!pipe->sspp)
- return -ENODEV;
+ num_lm = dpu_crtc_get_num_lm(crtc_state);
+ num_stages = (num_lm + 1) / PIPES_PER_STAGE;
+ for (stage_id = 0; stage_id < num_stages; stage_id++) {
+ i = stage_id * PIPES_PER_STAGE;
+ pipe = &pstate->pipe[i];
+ pipe_cfg = &pstate->pipe_cfg[i];
+ r_pipe = &pstate->pipe[i + 1];
+ r_pipe_cfg = &pstate->pipe_cfg[i + 1];
- if (!dpu_plane_try_multirect_parallel(pipe, pipe_cfg, r_pipe,
r_pipe_cfg,
- pipe->sspp,
-
msm_framebuffer_format(plane_state->fb),
-
dpu_kms->catalog->caps->max_linewidth)) {
- /* multirect is not possible, use two SSPP blocks */
- r_pipe->sspp = dpu_rm_reserve_sspp(&dpu_kms->rm, global_state,
crtc, &reqs);
- if (!r_pipe->sspp)
+ if (drm_rect_width(&pipe_cfg->src_rect) == 0)
+ goto r_pipe_assign;
+
+ pipe->sspp = dpu_rm_reserve_sspp(&dpu_kms->rm, global_state,
crtc, &reqs);
+ if (!pipe->sspp)
return -ENODEV;
- pipe->multirect_index = DPU_SSPP_RECT_SOLO;
- pipe->multirect_mode = DPU_SSPP_MULTIRECT_NONE;
+ /*
+ * Check multi-rect opportunity for the 2nd pipe in the
+ * pair. SSPP multi-rect mode cross mixer pairs is not
+ * supported.
+ */
+ if (drm_rect_width(&r_pipe_cfg->src_rect) != 0 &&
+ dpu_plane_try_multirect_parallel(pipe, pipe_cfg, r_pipe,
r_pipe_cfg,
+ pipe->sspp,
+
msm_framebuffer_format(plane_state->fb),
+
dpu_kms->catalog->caps->max_linewidth)) {
+ DPU_DEBUG_PLANE(pdpu, "allocate sspp_%d for pipe %d and
%d.\n",
+ pipe->sspp->idx - SSPP_NONE, i, i + 1);
+ continue;
+ }
+
+ DPU_DEBUG_PLANE(pdpu, "allocate sspp_%d for pipe %d\n",
+ pipe->sspp->idx - SSPP_NONE, i);
+
+r_pipe_assign:
+ if (drm_rect_width(&r_pipe_cfg->src_rect) == 0)
+ continue;
+
+ r_pipe->sspp = dpu_rm_reserve_sspp(&dpu_kms->rm,
+ global_state,
+ crtc, &reqs);
+ if (!r_pipe->sspp)
+ return -ENODEV;
- r_pipe->multirect_index = DPU_SSPP_RECT_SOLO;
- r_pipe->multirect_mode = DPU_SSPP_MULTIRECT_NONE;
+ DPU_DEBUG_PLANE(pdpu, "allocate sspp_%d for pipe %d\n",
+ r_pipe->sspp->idx - SSPP_NONE, i + 1);
}
return dpu_plane_atomic_check_sspp(plane, state, crtc_state);
--
2.34.1
