On DPU >= 5.0 CTL blocks were reworked in order to support using a
single CTL for all outputs. In preparation of reworking the RM code to
return single CTL make sure that dpu_encoder can cope with that.

Signed-off-by: Dmitry Baryshkov <dmitry.barysh...@linaro.org>
---
 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 6 +++++-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
index 
5172ab4dea995a154cd88d05c3842d7425fc34ce..666a755dc74b41b79fa1bb2878339592478e4333
 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
@@ -1283,7 +1283,11 @@ static void dpu_encoder_virt_atomic_mode_set(struct 
drm_encoder *drm_enc,
                        return;
                }
 
-               phys->hw_ctl = i < num_ctl ? to_dpu_hw_ctl(hw_ctl[i]) : NULL;
+               /* Use first (and only) CTL if active CTLs are supported */
+               if (num_ctl == 1)
+                       phys->hw_ctl = to_dpu_hw_ctl(hw_ctl[0]);
+               else
+                       phys->hw_ctl = i < num_ctl ? to_dpu_hw_ctl(hw_ctl[i]) : 
NULL;
                if (!phys->hw_ctl) {
                        DPU_ERROR_ENC(dpu_enc,
                                "no ctl block assigned at idx: %d\n", i);

-- 
2.39.5

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