On 2/14/2025 7:08 AM, Krzysztof Kozlowski wrote:
PHY_CMN_CLK_CFG1 register has four fields being used in the driver: DSI
clock divider, source of bitclk and two for enabling the DSI PHY PLL
clocks.
dsi_7nm_set_usecase() sets only the source of bitclk, so should leave
all other bits untouched. Use newly introduced
dsi_pll_cmn_clk_cfg1_update() to update respective bits without
overwriting the rest.
While shuffling the code, define and use PHY_CMN_CLK_CFG1 bitfields to
make the code more readable and obvious.
Fixes: 1ef7c99d145c ("drm/msm/dsi: add support for 7nm DSI PHY/PLL")
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlow...@linaro.org>
---
Changes in v3:
1. Define bitfields (move here parts from patch #4)
---
drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c | 4 ++--
drivers/gpu/drm/msm/registers/display/dsi_phy_7nm.xml | 1 +
2 files changed, 3 insertions(+), 2 deletions(-)
Reviewed-by: Abhinav Kumar <quic_abhin...@quicinc.com>
