On Tue, Jan 28, 2025 at 03:10:27PM -0800, Abhinav Kumar wrote:
> Widebus allows the DP controller to operate in 2 pixel per clock mode.
> The mode validation logic validates the mode->clock against the max
> DP pixel clock. However the max DP pixel clock limit assumes widebus
> is already enabled. Adjust the mode validation logic to only compare
> the adjusted pixel clock which accounts for widebus against the max DP
> pixel clock. Also fix the mode validation logic for YUV420 modes as in
> that case as well, only half the pixel clock is needed.
>
> Fixes: 757a2f36ab09 ("drm/msm/dp: enable widebus feature for display port")
> Fixes: 6db6e5606576 ("drm/msm/dp: change clock related programming for YUV420
> over DP")
> Signed-off-by: Abhinav Kumar <quic_abhin...@quicinc.com>
> ---
> drivers/gpu/drm/msm/dp/dp_display.c | 10 +++++-----
> drivers/gpu/drm/msm/dp/dp_drm.c | 5 ++++-
> 2 files changed, 9 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/msm/dp/dp_display.c
> b/drivers/gpu/drm/msm/dp/dp_display.c
> index
> 24dd37f1682bf5016bb0efbeb44489061deff060..a4b420a2d9eb7f084194f443e84a4013c9b4ef0f
> 100644
> --- a/drivers/gpu/drm/msm/dp/dp_display.c
> +++ b/drivers/gpu/drm/msm/dp/dp_display.c
> @@ -930,16 +930,16 @@ enum drm_mode_status msm_dp_bridge_mode_valid(struct
> drm_bridge *bridge,
> return -EINVAL;
> }
>
> - if (mode->clock > DP_MAX_PIXEL_CLK_KHZ)
> - return MODE_CLOCK_HIGH;
> -
> msm_dp_display = container_of(dp, struct msm_dp_display_private,
> msm_dp_display);
> link_info = &msm_dp_display->panel->link_info;
>
> - if (drm_mode_is_420_only(&dp->connector->display_info, mode) &&
> - msm_dp_display->panel->vsc_sdp_supported)
> + if ((drm_mode_is_420_only(&dp->connector->display_info, mode) &&
> + msm_dp_display->panel->vsc_sdp_supported) ||
> msm_dp_wide_bus_available(dp))
I'd ask to move msm_dp_wide_bus_available to the next line, it makes it
easier to read.
With that fixed:
Reviewed-by: Dmitry Baryshkov <dmitry.barysh...@linaro.org>
> mode_pclk_khz /= 2;
>
> + if (mode_pclk_khz > DP_MAX_PIXEL_CLK_KHZ)
> + return MODE_CLOCK_HIGH;
> +
> mode_bpp = dp->connector->display_info.bpc * num_components;
> if (!mode_bpp)
> mode_bpp = default_bpp;
> diff --git a/drivers/gpu/drm/msm/dp/dp_drm.c b/drivers/gpu/drm/msm/dp/dp_drm.c
> index
> d3e241ea6941615b8e274dd17426c2f8557f09b5..16b7913d1eefa8c2deb44df201a1977db23f4531
> 100644
> --- a/drivers/gpu/drm/msm/dp/dp_drm.c
> +++ b/drivers/gpu/drm/msm/dp/dp_drm.c
> @@ -257,7 +257,10 @@ static enum drm_mode_status
> msm_edp_bridge_mode_valid(struct drm_bridge *bridge,
> return -EINVAL;
> }
>
> - if (mode->clock > DP_MAX_PIXEL_CLK_KHZ)
> + if (msm_dp_wide_bus_available(dp))
> + mode_pclk_khz /= 2;
> +
> + if (mode_pclk_khz > DP_MAX_PIXEL_CLK_KHZ)
> return MODE_CLOCK_HIGH;
>
> /*
>
> ---
> base-commit: 2bd7708f11777d4fd436fcba62b57cff6a92e389
> change-id: 20250127-dp-widebus-fix-fba78bbe242d
>
> Best regards,
> --
> Abhinav Kumar <quic_abhin...@quicinc.com>
>
--
With best wishes
Dmitry
