On Mon, Dec 16, 2024 at 04:43:30PM -0800, Jessica Zhang wrote: > Cache the CWB block mask in the DPU virtual encoder and configure CWB > according to the CWB block mask within the writeback phys encoder > > Signed-off-by: Jessica Zhang <quic_jessz...@quicinc.com> > --- > drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 75 > +++++++++++++++++++++- > drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h | 7 +- > .../gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c | 4 +- > 3 files changed, 83 insertions(+), 3 deletions(-) >
Reviewed-by: Dmitry Baryshkov <dmitry.barysh...@linaro.org> -- With best wishes Dmitry
