On Fri, 29 Nov 2024 at 09:59, Xiangxu Yin <quic_xiang...@quicinc.com> wrote:
>
> Introduce a maximum width constraint for modes during validation. This
> ensures that the modes are filtered based on hardware capabilities,
> specifically addressing the line buffer limitations of individual pipes.
This doesn't describe, why this is necessary. What does "buffer
limitations of individual pipes" mean?
If the platforms have hw capabilities like being unable to support 8k
or 10k, it should go to platform data
>
> Signed-off-by: Xiangxu Yin <quic_xiang...@quicinc.com>
> ---
> drivers/gpu/drm/msm/dp/dp_display.c | 3 +++
> drivers/gpu/drm/msm/dp/dp_display.h | 1 +
> drivers/gpu/drm/msm/dp/dp_panel.c | 13 +++++++++++++
> drivers/gpu/drm/msm/dp/dp_panel.h | 1 +
> 4 files changed, 18 insertions(+)
>
> diff --git a/drivers/gpu/drm/msm/dp/dp_display.c
> b/drivers/gpu/drm/msm/dp/dp_display.c
> index
> 4c83402fc7e0d41cb7621fa2efda043269d0a608..eb6fb76c68e505fafbec563440e9784f51e1894b
> 100644
> --- a/drivers/gpu/drm/msm/dp/dp_display.c
> +++ b/drivers/gpu/drm/msm/dp/dp_display.c
> @@ -944,6 +944,9 @@ enum drm_mode_status msm_dp_bridge_mode_valid(struct
> drm_bridge *bridge,
> msm_dp_display = container_of(dp, struct msm_dp_display_private,
> msm_dp_display);
> link_info = &msm_dp_display->panel->link_info;
>
> + if (mode->hdisplay > msm_dp_display->panel->max_dp_width)
> + return MODE_BAD;
> +
> if (drm_mode_is_420_only(&dp->connector->display_info, mode) &&
> msm_dp_display->panel->vsc_sdp_supported)
> mode_pclk_khz /= 2;
> diff --git a/drivers/gpu/drm/msm/dp/dp_display.h
> b/drivers/gpu/drm/msm/dp/dp_display.h
> index
> ecbc2d92f546a346ee53adcf1b060933e4f54317..7a11f7eeb691976f06afc7aff67650397d7deb90
> 100644
> --- a/drivers/gpu/drm/msm/dp/dp_display.h
> +++ b/drivers/gpu/drm/msm/dp/dp_display.h
> @@ -11,6 +11,7 @@
> #include "disp/msm_disp_snapshot.h"
>
> #define DP_MAX_PIXEL_CLK_KHZ 675000
> +#define DP_MAX_WIDTH 7680
>
> struct msm_dp {
> struct drm_device *drm_dev;
> diff --git a/drivers/gpu/drm/msm/dp/dp_panel.c
> b/drivers/gpu/drm/msm/dp/dp_panel.c
> index
> 8654180aa259234bbd41f4f88c13c485f9791b1d..10501e301c5e073d8d34093b86a15d72e646a01f
> 100644
> --- a/drivers/gpu/drm/msm/dp/dp_panel.c
> +++ b/drivers/gpu/drm/msm/dp/dp_panel.c
> @@ -4,6 +4,7 @@
> */
>
> #include "dp_panel.h"
> +#include "dp_display.h"
> #include "dp_utils.h"
>
> #include <drm/drm_connector.h>
> @@ -455,6 +456,16 @@ static u32 msm_dp_panel_link_frequencies(struct
> device_node *of_node)
> return frequency;
> }
>
> +static u32 msm_dp_panel_max_width(struct device_node *of_node)
> +{
> + u32 max_width = 0;
> +
> + if (of_property_read_u32(of_node, "max-width", &max_width))
> + max_width = DP_MAX_WIDTH;
> +
> + return max_width;
msm_dp_panel->max_dp_width = DP_MAX_WIDTH;
of_property_read_u32(of_node, "max-width", &msm_dp_panel->max_dp_width);
> +}
> +
> static int msm_dp_panel_parse_dt(struct msm_dp_panel *msm_dp_panel)
> {
> struct msm_dp_panel_private *panel;
> @@ -490,6 +501,8 @@ static int msm_dp_panel_parse_dt(struct msm_dp_panel
> *msm_dp_panel)
> if (!msm_dp_panel->max_dp_link_rate)
> msm_dp_panel->max_dp_link_rate = DP_LINK_RATE_HBR2;
>
> + msm_dp_panel->max_dp_width = msm_dp_panel_max_width(of_node);
> +
> return 0;
> }
>
> diff --git a/drivers/gpu/drm/msm/dp/dp_panel.h
> b/drivers/gpu/drm/msm/dp/dp_panel.h
> index
> 7603b92c32902bd3d4485539bd6308537ff75a2c..61513644161209c243bbb623ee4ded951b2a0597
> 100644
> --- a/drivers/gpu/drm/msm/dp/dp_panel.h
> +++ b/drivers/gpu/drm/msm/dp/dp_panel.h
> @@ -51,6 +51,7 @@ struct msm_dp_panel {
> u32 lane_map[DP_MAX_NUM_DP_LANES];
> u32 max_dp_lanes;
> u32 max_dp_link_rate;
> + u32 max_dp_width;
>
> u32 max_bw_code;
> };
>
> --
> 2.25.1
>
--
With best wishes
Dmitry
