On Tue, 26 Nov 2024 at 17:37, Akhil P Oommen <quic_akhi...@quicinc.com> wrote:
>
> On 11/25/2024 10:16 PM, Dmitry Baryshkov wrote:
> > On Mon, Nov 25, 2024 at 10:03:00PM +0530, Akhil P Oommen wrote:
> >> There are a few chipsets which don't have system cache a.k.a LLC.
> >> Currently, the assumption in the driver is that the system cache
> >> availability correlates with the presence of GMU or RPMH, which
> >> is not true. For instance, Snapdragon 6 Gen 1 has RPMH and a GPU
> >> with a full blown GMU, but doesnot have a system cache. So,
> >> introduce an Adreno Quirk flag to check support for system cache
> >> instead of using gmu_wrapper flag.
> >>
> >> Signed-off-by: Akhil P Oommen <quic_akhi...@quicinc.com>
> >> ---
> >> drivers/gpu/drm/msm/adreno/a6xx_catalog.c | 3 ++-
> >> drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 7 +------
> >> drivers/gpu/drm/msm/adreno/adreno_gpu.h | 1 +
> >> 3 files changed, 4 insertions(+), 7 deletions(-)
> >>
> >> diff --git a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c
> >> b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c
> >> index 0c560e84ad5a..5e389f6b8b8a 100644
> >> --- a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c
> >> +++ b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c
> >> @@ -682,6 +682,7 @@ static const struct adreno_info a6xx_gpus[] = {
> >> },
> >> .gmem = (SZ_128K + SZ_4K),
> >> .inactive_period = DRM_MSM_INACTIVE_PERIOD,
> >> + .quirks = ADRENO_QUIRK_NO_SYSCACHE,
> >> .init = a6xx_gpu_init,
> >> .zapfw = "a610_zap.mdt",
> >> .a6xx = &(const struct a6xx_info) {
> >> @@ -1331,7 +1332,7 @@ static const struct adreno_info a7xx_gpus[] = {
> >> },
> >> .gmem = SZ_128K,
> >> .inactive_period = DRM_MSM_INACTIVE_PERIOD,
> >> - .quirks = ADRENO_QUIRK_HAS_HW_APRIV,
> >> + .quirks = ADRENO_QUIRK_HAS_HW_APRIV |
> >> ADRENO_QUIRK_NO_SYSCACHE,
> >> .init = a6xx_gpu_init,
> >> .zapfw = "a702_zap.mbn",
> >> .a6xx = &(const struct a6xx_info) {
> >> diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
> >> b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
> >> index 019610341df1..a8b928d0f320 100644
> >> --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
> >> +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
> >> @@ -1863,10 +1863,6 @@ static void a7xx_llc_activate(struct a6xx_gpu
> >> *a6xx_gpu)
> >>
> >> static void a6xx_llc_slices_destroy(struct a6xx_gpu *a6xx_gpu)
> >> {
> >> - /* No LLCC on non-RPMh (and by extension, non-GMU) SoCs */
> >> - if (adreno_has_gmu_wrapper(&a6xx_gpu->base))
> >> - return;
> >> -
> >
> > Shouldn't it also be a NO_SYSCACHE check?
>
> llcc_slice_putd() has an ERR_OR_NULL check inside. So, not really needed.
Reviewed-by: Dmitry Baryshkov <dmitry.barysh...@linaro.org>
>
> -Akhil.
> >
> >> llcc_slice_putd(a6xx_gpu->llc_slice);
> >> llcc_slice_putd(a6xx_gpu->htw_llc_slice);
> >> }
> >> @@ -1876,8 +1872,7 @@ static void a6xx_llc_slices_init(struct
> >> platform_device *pdev,
> >> {
> >> struct device_node *phandle;
> >>
> >> - /* No LLCC on non-RPMh (and by extension, non-GMU) SoCs */
> >> - if (adreno_has_gmu_wrapper(&a6xx_gpu->base))
> >> + if (a6xx_gpu->base.info->quirks & ADRENO_QUIRK_NO_SYSCACHE)
> >> return;
> >>
> >> /*
> >> diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h
> >> b/drivers/gpu/drm/msm/adreno/adreno_gpu.h
> >> index e71f420f8b3a..398be2218110 100644
> >> --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h
> >> +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h
> >> @@ -57,6 +57,7 @@ enum adreno_family {
> >> #define ADRENO_QUIRK_HAS_HW_APRIV BIT(3)
> >> #define ADRENO_QUIRK_HAS_CACHED_COHERENT BIT(4)
> >> #define ADRENO_QUIRK_PREEMPTION BIT(5)
> >> +#define ADRENO_QUIRK_NO_SYSCACHE BIT(6)
> >>
> >> /* Helper for formating the chip_id in the way that userspace tools like
> >> * crashdec expect.
> >>
> >> --
> >> 2.45.2
> >>
> >
>
--
With best wishes
Dmitry
