On Wed, Oct 09, 2024 at 04:50:27PM GMT, Jun Nie wrote:
> Request 4 mixers and 4 DSC for the case that both dual-DSI and DSC are
> enabled. We prefer to use 4 pipes for dual DSI case for it is power optimal
> for DSC.
> 
> Signed-off-by: Jun Nie <jun....@linaro.org>
> ---
>  drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c         |  2 +-
>  drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h         |  6 ++---
>  drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c      | 29 
> ++++++++++++++++++------
>  drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h |  3 ++-
>  drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h   |  1 +
>  drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h      |  2 +-
>  6 files changed, 30 insertions(+), 13 deletions(-)
> 
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c 
> b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
> index d2aca0a9493d5..dbdfff1c7792a 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
> @@ -200,7 +200,7 @@ static int dpu_crtc_get_lm_crc(struct drm_crtc *crtc,
>               struct dpu_crtc_state *crtc_state)
>  {
>       struct dpu_crtc_mixer *m;
> -     u32 crcs[CRTC_DUAL_MIXERS];
> +     u32 crcs[CRTC_QUAD_MIXERS];
>  
>       int rc = 0;
>       int i;
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h 
> b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h
> index ee7cf71f89fc7..f8276afd99192 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h
> @@ -211,7 +211,7 @@ struct dpu_crtc_state {
>  
>       bool bw_control;
>       bool bw_split_vote;
> -     struct drm_rect lm_bounds[CRTC_DUAL_MIXERS];
> +     struct drm_rect lm_bounds[CRTC_QUAD_MIXERS];
>  
>       uint64_t input_fence_timeout_ns;
>  
> @@ -219,10 +219,10 @@ struct dpu_crtc_state {
>  
>       /* HW Resources reserved for the crtc */
>       u32 num_mixers;
> -     struct dpu_crtc_mixer mixers[CRTC_DUAL_MIXERS];
> +     struct dpu_crtc_mixer mixers[CRTC_QUAD_MIXERS];
>  
>       u32 num_ctls;
> -     struct dpu_hw_ctl *hw_ctls[CRTC_DUAL_MIXERS];
> +     struct dpu_hw_ctl *hw_ctls[CRTC_QUAD_MIXERS];
>  
>       u32 num_dscs;
>       enum dpu_crtc_crc_source crc_source;
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c 
> b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
> index 68655c8817bf8..ed220ac691e8a 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
> @@ -54,7 +54,7 @@
>  #define MAX_PHYS_ENCODERS_PER_VIRTUAL \
>       (MAX_H_TILES_PER_DISPLAY * NUM_PHYS_ENCODER_TYPES)
>  
> -#define MAX_CHANNELS_PER_ENC 2
> +#define MAX_CHANNELS_PER_ENC 4
>  
>  #define IDLE_SHORT_TIMEOUT   1
>  
> @@ -588,15 +588,19 @@ static struct msm_display_topology 
> dpu_encoder_get_topology(
>  
>       /* Datapath topology selection
>        *
> -      * Dual display
> +      * Dual display without DSC
>        * 2 LM, 2 INTF ( Split display using 2 interfaces)
>        *
> +      * Dual display with DSC
> +      * 4 LM, 2 INTF ( Split display using 2 interfaces)
> +      *
>        * Single display
>        * 1 LM, 1 INTF
>        * 2 LM, 1 INTF (stream merge to support high resolution interfaces)
>        *
>        * Add dspps to the reservation requirements if ctm is requested
>        */
> +
>       if (intf_count == 2)
>               topology.num_lm = 2;
>       else if (!dpu_kms->catalog->caps->has_3d_merge)
> @@ -615,10 +619,21 @@ static struct msm_display_topology 
> dpu_encoder_get_topology(
>                * 2 DSC encoders, 2 layer mixers and 1 interface
>                * this is power optimal and can drive up to (including) 4k
>                * screens
> +              * But for dual display case, we prefer 4 layer mixers. Because
> +              * the resolution is always high in the case and 4 DSCs are more
> +              * power optimal. While a single SSPP can only co-work with one
> +              * mixer pair. So 4 mixers are needed in this case.

What is the relationship between SSPP working with a mixer pair and
high-res using 4 mixers? You have been writing about DSC, then you
suddently mention SSPP.

>                */
> -             topology.num_dsc = 2;
> -             topology.num_lm = 2;
> -             topology.num_intf = 1;
> +
> +             if (intf_count == 2) {
> +                     topology.num_dsc = 4;
> +                     topology.num_lm = 4;
> +                     topology.num_intf = 2;
> +             } else {
> +                     topology.num_dsc = 2;
> +                     topology.num_lm = 2;
> +                     topology.num_intf = 1;
> +             }
>       }
>  
>       return topology;
> @@ -2031,8 +2046,8 @@ static void dpu_encoder_helper_reset_mixers(struct 
> dpu_encoder_phys *phys_enc)
>       struct dpu_hw_mixer_cfg mixer;
>       int i, num_lm;
>       struct dpu_global_state *global_state;
> -     struct dpu_hw_blk *hw_lm[2];
> -     struct dpu_hw_mixer *hw_mixer[2];
> +     struct dpu_hw_blk *hw_lm[MAX_CHANNELS_PER_ENC];
> +     struct dpu_hw_mixer *hw_mixer[MAX_CHANNELS_PER_ENC];
>       struct dpu_hw_ctl *ctl = phys_enc->hw_ctl;
>  
>       memset(&mixer, 0, sizeof(mixer));
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h 
> b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h
> index e77ebe3a68da9..c877ee45535ac 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h
> @@ -324,7 +324,8 @@ static inline enum dpu_3d_blend_mode 
> dpu_encoder_helper_get_3d_blend_mode(
>  
>       /* Use merge_3d unless DSC MERGE topology is used */
>       if (phys_enc->split_role == ENC_ROLE_SOLO &&
> -         dpu_cstate->num_mixers == CRTC_DUAL_MIXERS &&
> +         (dpu_cstate->num_mixers == CRTC_DUAL_MIXERS ||
> +             dpu_cstate->num_mixers == CRTC_QUAD_MIXERS) &&
>           !dpu_encoder_use_dsc_merge(phys_enc->parent))
>               return BLEND_3D_H_ROW_INT;
>  
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h 
> b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
> index bf86d643887dd..f79ecd409a830 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
> @@ -25,6 +25,7 @@
>  #define MAX_IMG_HEIGHT 0x3fff
>  
>  #define CRTC_DUAL_MIXERS     2
> +#define CRTC_QUAD_MIXERS     4
>  
>  #define MAX_XIN_COUNT 16
>  
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h 
> b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h
> index d8f5cffa60ea6..671e03406df74 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h
> @@ -32,9 +32,9 @@
>  #define DPU_MAX_PLANES                       4
>  #endif
>  
> -#define PIPES_PER_PLANE                      2
>  #define PIPES_PER_LM_PAIR            2
>  #define LM_PAIRS_PER_PLANE           2
> +#define PIPES_PER_PLANE                      (PIPES_PER_LM_PAIR * 
> LM_PAIRS_PER_PLANE)
>  #ifndef DPU_MAX_DE_CURVES
>  #define DPU_MAX_DE_CURVES            3
>  #endif
> 
> -- 
> 2.34.1
> 

-- 
With best wishes
Dmitry

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