On 4/17/2023 1:21 PM, Marijn Suijten wrote:
Neither of these SoCs has INTF0, they only have a DSI interface on index
1. Stop enabling an interrupt that can't fire.
Fixes: 3581b7062cec ("drm/msm/disp/dpu1: add support for display on SM6115")
Fixes: 5334087ee743 ("drm/msm: add support for QCM2290 MDSS")
Signed-off-by: Marijn Suijten <marijn.suij...@somainline.org>
Reviewed-by: Dmitry Baryshkov <dmitry.barysh...@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dyb...@linaro.org>
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Yes, this is right, Both of these chipsets only have DSI on index 1.
Reviewed-by: Abhinav Kumar <quic_abhin...@quicinc.com>
