[Freedreno] [PATCH v6 3/4] drm/msm/dp: parser link-frequencies as property of dp_out endpoint

[Kuogee Hsieh]

Add capability to parser and retrieve max DP link supported rate from
link-frequencies property of dp_out endpoint.

Changes in v6:
-- second patch after split parser patch into two patches

Signed-off-by: Kuogee Hsieh <quic_khs...@quicinc.com>
---
 drivers/gpu/drm/msm/dp/dp_parser.c | 16 ++++++++++++++++
 drivers/gpu/drm/msm/dp/dp_parser.h |  2 ++
 2 files changed, 18 insertions(+)

diff --git a/drivers/gpu/drm/msm/dp/dp_parser.c 
b/drivers/gpu/drm/msm/dp/dp_parser.c
index b06ff60..2006341 100644
--- a/drivers/gpu/drm/msm/dp/dp_parser.c
+++ b/drivers/gpu/drm/msm/dp/dp_parser.c
@@ -95,6 +95,7 @@ static int dp_parser_misc(struct dp_parser *parser)
 {
        struct device_node *of_node = parser->pdev->dev.of_node;
        struct device_node *endpoint;
+       u64 frequency;
        int cnt;
 
        /*
@@ -103,6 +104,7 @@ static int dp_parser_misc(struct dp_parser *parser)
        cnt = drm_of_get_data_lanes_count(of_node, 1, DP_MAX_NUM_DP_LANES);
        if (cnt > 0) {
                parser->max_dp_lanes = cnt;
+               parser->max_dp_link_rate = DP_LINK_RATE_HBR2; /* 540000 khz */
                return 0;
        }
 
@@ -116,8 +118,22 @@ static int dp_parser_misc(struct dp_parser *parser)
                        parser->max_dp_lanes = DP_MAX_NUM_DP_LANES; /* 4 lanes 
*/
                else
                        parser->max_dp_lanes = cnt;
+
+               cnt = of_property_count_u64_elems(endpoint, "link-frequencies");
+               if (cnt < 0) {
+                       parser->max_dp_link_rate = DP_LINK_RATE_HBR2; /* 540000 
khz */
+               } else {
+                       if (cnt > DP_MAX_NUM_DP_LANES)
+                               cnt = DP_MAX_NUM_DP_LANES;
+
+                       of_property_read_u64_index(endpoint, "link-frequencies",
+                                                       cnt - 1, &frequency);
+
+                       parser->max_dp_link_rate = (frequency / 1000); /* kbits 
*/
+               }
        } else {
                parser->max_dp_lanes = DP_MAX_NUM_DP_LANES; /* 4 lanes */
+               parser->max_dp_link_rate = DP_LINK_RATE_HBR2; /* 540000 khz */
        }
 
        return 0;
diff --git a/drivers/gpu/drm/msm/dp/dp_parser.h 
b/drivers/gpu/drm/msm/dp/dp_parser.h
index 866c1a8..3ddf639 100644
--- a/drivers/gpu/drm/msm/dp/dp_parser.h
+++ b/drivers/gpu/drm/msm/dp/dp_parser.h
@@ -15,6 +15,7 @@
 #define DP_LABEL "MDSS DP DISPLAY"
 #define DP_MAX_PIXEL_CLK_KHZ   675000
 #define DP_MAX_NUM_DP_LANES    4
+#define DP_LINK_RATE_HBR2       540000
 
 enum dp_pm_type {
        DP_CORE_PM,
@@ -119,6 +120,7 @@ struct dp_parser {
        struct dp_io io;
        struct dp_display_data disp_data;
        u32 max_dp_lanes;
+       u32 max_dp_link_rate;
        struct drm_bridge *next_bridge;
 
        int (*parse)(struct dp_parser *parser);
-- 
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