On Mon, 21 Mar 2022 at 19:21, Vinod Polimera <[email protected]> wrote: > > > > > -----Original Message----- > > From: Stephen Boyd <[email protected]> > > Sent: Friday, March 18, 2022 2:41 AM > > To: quic_vpolimer <[email protected]>; > > [email protected]; [email protected]; > > [email protected]; [email protected] > > Cc: [email protected]; [email protected]; > > [email protected]; [email protected]; quic_kalyant > > <[email protected]> > > Subject: Re: [PATCH v6 1/5] drm/msm/disp/dpu1: set mdp clk to the > > maximum frequency in opp table during probe > > > > WARNING: This email originated from outside of Qualcomm. Please be wary > > of any links or attachments, and do not enable macros. > > > > Quoting Vinod Polimera (2022-03-14 07:46:53) > > > use max clock during probe/bind sequence from the opp table. > > > The clock will be scaled down when framework sends an update. > > > > Capitalize 'use'. > > > > Why is it important to use max frequency during probe/bind? Does not > > setting the clk rate during probe mean that we'll never use the max > > rate? Does it speed things up during probe? > > We need to vote mdp clock during probe/bind so that rails are not set at > undetermined state as pointed out by Dmitry. > Since we dont know what will be the rate set in boot loader, it would be > ideal to vote at max frequency. > There could be a firmware display programmed in bootloader and we want to > transition it to kernel without underflowing.
This should be expressed in the commit message. -- With best wishes Dmitry
