Quoting Vinod Polimera (2022-02-21 05:12:06) > Panels with higher refresh rate will need mdp clk above 300Mhz. > Select max frequency for mdp clock during bootup, dpu driver will > scale down the clock as per usecase when first update from the framework is > received. > > Signed-off-by: Vinod Polimera <quic_vpoli...@quicinc.com>
Please add a Fixes tag. > --- > arch/arm64/boot/dts/qcom/sc7280.dtsi | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi > b/arch/arm64/boot/dts/qcom/sc7280.dtsi > index baf1653..7af96fc 100644 > --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi > +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi > @@ -2895,7 +2895,7 @@ > assigned-clocks = <&dispcc > DISP_CC_MDSS_MDP_CLK>, > <&dispcc > DISP_CC_MDSS_VSYNC_CLK>, > <&dispcc > DISP_CC_MDSS_AHB_CLK>; > - assigned-clock-rates = <300000000>, > + assigned-clock-rates = <506666667>, Why not simply remove the clock assignment and set the rate based on the OPP when the driver probes? > <19200000>, > <19200000>; > operating-points-v2 = <&mdp_opp_table>;
