on 27/09/2009 15:17 Andriy Gapon said the following:
> Another idea of working around this:
> 1) in pci fixup code disable USB SMI for these chipsets
> 2) (optional) in ohci code skip takeover step
> Sounds messy.
BTW, just for the sake of experiment I did exactly what I suggested.
I've got the following messages:
kernel: ohci_controller_init:195: SMM active, request owner change
kernel: usbus0: SMM does not respond, resetting
kernel: ohci_controller_init:195: SMM active, request owner change
kernel: usbus1: SMM does not respond, resetting
kernel: ohci_controller_init:195: SMM active, request owner change
kernel: usbus3: SMM does not respond, resetting
kernel: ohci_controller_init:195: SMM active, request owner change
kernel: usbus4: SMM does not respond, resetting
kernel: ohci_controller_init:195: SMM active, request owner change
kernel: usbus6: SMM does not respond, resetting
And the register value stayed intact after initial programming, so no
re-programming was needed.
Here is the (dirty) hack:
diff --git a/sys/dev/pci/fixup_pci.c b/sys/dev/pci/fixup_pci.c
index 566e503..1463c24 100644
--- a/sys/dev/pci/fixup_pci.c
+++ b/sys/dev/pci/fixup_pci.c
@@ -53,6 +53,7 @@ static int fixup_pci_probe(device_t dev);
static void fixwsc_natoma(device_t dev);
static void fixc1_nforce2(device_t dev);
static void fixrtc_piix4(device_t dev);
+static void fixsmi_usb(device_t dev);
static device_method_t fixup_pci_methods[] = {
/* Device interface */
@@ -84,6 +85,9 @@ fixup_pci_probe(device_t dev)
case 0x01e010de: /* nVidia nForce2 */
fixc1_nforce2(dev);
break;
+ case 0x96001022: /* AMD SB700 */
+ fixsmi_usb(dev);
+ break;
}
return(ENXIO);
}
@@ -124,6 +128,21 @@
}
+/* Disable USB SMI */
+static void
+fixsmi_usb(device_t dev)
+{
+ uint32_t features;
+
+ dev = pci_find_device(0x1002, 0x4385);
+ features = pci_read_config(dev, 0x64, 4);
+ if (features & (1 << 15)) {
+ printf("Disabling USB SMI on SB7xx\n");
+ features &= ~(1 << 15);
+ pci_write_config(dev, 0x64, features, 4);
+ }
+}
+
/*
* Set the SYSTEM_IDLE_TIMEOUT to 80 ns on nForce2 systems to work
* around a hang that is triggered when the CPU generates a very fast
--
Andriy Gapon
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