Hi,
While trying to build assorted ports on RISC-V I found that devel/glib20
doesn’t build.
It turns out to be due to a missing __GCC_HAVE_SYNC_COMPARE_AND_SWAP_4
define. That define is implicitly set by the toolchain. Or, at least, it
is on other platforms (ARM, MIPS, x86, …), but not on RISC-V.
That’s likely just been forgotten. The following toolchain patch fixes
that for me:
diff --git a/contrib/llvm-project/clang/lib/Basic/Targets/RISCV.cpp
b/contrib/llvm-project/clang/lib/Basic/Targets/RISCV.cpp
index 4ba703c8dd1..73f1b5bc446 100644
--- a/contrib/llvm-project/clang/lib/Basic/Targets/RISCV.cpp
+++ b/contrib/llvm-project/clang/lib/Basic/Targets/RISCV.cpp
@@ -115,8 +115,14 @@ void RISCVTargetInfo::getTargetDefines(const
LangOptions &Opts,
Builder.defineMacro("__riscv_muldiv");
}
- if (HasA)
+ if (HasA) {
Builder.defineMacro("__riscv_atomic");
+ Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1");
+ Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2");
+ Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4");
+ if (Is64Bit)
+ Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8");
+ }
if (HasF || HasD) {
Builder.defineMacro("__riscv_flen", HasD ? "64" : "32");
Best regards,
Kristof
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