Ok, I was not sure if this was a "No news is good news" request.
Attached are the lspci:s of the MB and devices I have had the pleasure of
testing. I have found nothing bad on these once but please remember that I
had to hack the nVidia MCP67-A1 to have it accepted as a SATA and AHCI
controller.
All controllers have had large copy in/out, backups at file-system level
via dump/zfs snapshot and tar and all have had bonny++ tests done.
On AHCI controllers, I have at least remove and re-inserted one disk of a
zpool.
Cheers,
Göran
Best regards,
Göran L
--On October 16, 2008 13:15:46 +0400 "Andrey V. Elsukov"
<[EMAIL PROTECTED]> wrote:
Jeremy Chadwick wrote:
- Could someone provide an explanation of the 48-bit LBA addressing
changes (see lines 988-1003 in the patch)? I'd like to know what they
do, and if further QA/testing is needed with this.
I think this is for debug purposes.
- Can we please see about adding the FreeNAS project's ata timeout
sysctls? I see lots of delays/sleeps in numerous pieces of code that
pertain to soft or hard resets of AHCI controllers, and I often worry
about the implications of hard-coded timeouts.
http://freenas.svn.sourceforge.net/viewvc/freenas/trunk/build/kernel-p
atches/ata/files/patch-ata.diff?view=markup
As i remember changes in FreeNAS don't change timeouts for resets.
In any case, these changes can not be in 7.1-RELEASE. My patch
targeted to move changes from CURRENT to 7.1. But it seems there
are too few testers and patch can not be commited.
--
WBR, Andrey V. Elsukov
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