Hello,
I'd like to summit a patch that fixes a hanging issue related to Rx FIFO
overrun on the following chips and rev (tested):
ID:
CHIP_ID_YUKON_EC
REV:
CHIP_REV_YU_EC_A2
CHIP_REV_YU_EC_A3
(I haven't tested it on CHIP_REV_YU_EC_A1)
@@ -3813,16 +3805,24 @@
GMR_FS_ANY_ERR);
}
- /*
- * Set Rx FIFO flush threshold to 64 bytes + 1 FIFO word
- * due to hardware hang on receipt of pause frames.
- */
- reg = RX_GMF_FL_THR_DEF + 1;
- /* Another magic for Yukon FE+ - From Linux. */
- if (sc->msk_hw_id == CHIP_ID_YUKON_FE_P &&
- sc->msk_hw_rev == CHIP_REV_YU_FE_P_A0)
- reg = 0x178;
- CSR_WRITE_2(sc, MR_ADDR(sc_if->msk_port, RX_GMF_FL_THR), reg);
+ if (sc->msk_hw_id == CHIP_ID_YUKON_EC){
+ /* Set Rx FIFO flush threshold to 64 bytes. */
+ CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_FL_THR),
+ RX_GMF_FL_THR_DEF);
+ }
+ else {
+ /*
+ * Set Rx FIFO flush threshold to 64 bytes + 1 FIFO word
+ * due to hardware hang on receipt of pause frames.
+ */
+ reg = RX_GMF_FL_THR_DEF + 1;
+ /* Another magic for Yukon FE+ - From Linux. */
+ if (sc->msk_hw_id == CHIP_ID_YUKON_FE_P &&
+ sc->msk_hw_rev == CHIP_REV_YU_FE_P_A0)
+ reg = 0x178;
+ CSR_WRITE_2(sc, MR_ADDR(sc_if->msk_port, RX_GMF_FL_THR), reg);
+ }
/* Configure Tx MAC FIFO. */
CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T),
GMF_RST_SET);
The symptoms of the problem was that if a large amount of small TCP
packets were fired up at the interface it would generate an interrupt
from MAC1 with a GMAC status of 0x7 and while the chip Tx would still
function the Rx would 'hang'. Triggering a watchdog timeout would make
it work again sometimes but calling mskc_reset() didn't worked at all.
It turned out that we had an old driver written by Pyun YongHyeon that
would work flawlessly on that chip. This patch helps support that old chip.
I hope this helps someone,
Karim.
PS: The patch line numbers are against 'CURRENT' r214406 but should also
apply to FBSD 7 and 8.
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