Bruce Evans writes:
> > Is there an issue on non-x86 architectures?
>
> Not AFAIK. Not far, but SMP and FreeBSD's ithread implementation need
> something like an x86 ICU to work right. The interrupt mask must be
> global, and per-cpu ipls don't (naturally) work right even in the 1-cpu
> case since they are designed for masking interrupts in a nested way with
> the CPU determining the prioritization, but ithreads are non-nested and
> want their own prioritization.
>
> Bruce
On 5.0 alpha, when an non-fast interrupt is dispatched, the device
interrupt is disabled in the hardware. Eg, for PC like machines,
interrupts are disabled/re-enabled each time an interrupt fires via
isa_{en,dis}able_intr() in alpha/isa/isa.c. Other platforms have
their own way of doing the same thing. In retrospect, this seems to
be hideously expensive...
In 4.x, there is no SMP on alpha and the IPL level is raised when a
device interrupt handler is run, so that the handler can never be
interrupted by the device itself.
Drew
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