> > >
> > > The reason why it is not working is almost certainly in the driver.
> > >
> > > There are two kinds of cables used with these cards.
> > > SDL Communications, the manufacturer, supplies x.21 cables
> > > that have the input clock pin tied to the output clock pin.
> > >
> > > Normaly I should be able to use a driver option to tell the
> > > HDLC chip to pass the signal through to the output clock pin.
>
> This is now working properly, to adapt the driver if_sr.c to my case,
> a global variable (My_Case) has to be added in
> sr_init_msci(structsr_softc *sc):
Oops! It looks like you found the bug. It is amazing that the driver
have lived so long with this. My test setup is much too forgiving. :-/
Can you try this (untested) patch and see if it still works, please?
This is basically the same I as have it in the ar(4) driver.
Thanks.
John
--
John Hay -- [EMAIL PROTECTED]
--- if_sr.c.org Tue May 16 12:48:41 2000
+++ if_sr.c Thu Feb 22 20:04:23 2001
@@ -1815,8 +1815,10 @@
printf("sr%d: External Clock Selected.\n", portndx);
#endif
- SRC_PUT8(hc->sca_base, msci->rxs, 0);
- SRC_PUT8(hc->sca_base, msci->txs, 0);
+ SRC_PUT8(hc->sca_base, msci->rxs,
+ SCA_RXS_CLK_RXC0 | SCA_RXS_DIV1);
+ SRC_PUT8(hc->sca_base, msci->txs,
+ SCA_TXS_CLK_RX | SCA_TXS_DIV1);
break;
case SR_FLAGS_EXT_SEP_CLK:
@@ -1824,20 +1826,10 @@
printf("sr%d: Split Clocking Selected.\n", portndx);
#endif
-#if 1
- SRC_PUT8(hc->sca_base, msci->rxs, 0);
- SRC_PUT8(hc->sca_base, msci->txs, 0);
-#else
SRC_PUT8(hc->sca_base, msci->rxs,
SCA_RXS_CLK_RXC0 | SCA_RXS_DIV1);
-
- /*
- * We need to configure the internal bit clock for the
- * transmitter's channel...
- */
SRC_PUT8(hc->sca_base, msci->txs,
- SCA_TXS_CLK_RX | SCA_TXS_DIV1);
-#endif
+ SCA_TXS_CLK_TXC | SCA_TXS_DIV1);
break;
case SR_FLAGS_INT_CLK:
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