On Thu, Oct 09, 2003 at 07:24:15PM +0200, Bernd Walter wrote:
>> Note that, possibly contrary to expectations, 8-bit and 16-bit
>> _writes_ are not atomic on many (all?) the 64-bit architectures.
>> Small writes are generally done by doing a 64-bit read, insert
>> under mask and 64-bit write.
>
>The mask case is true - e.g. on alpha <=ev5, but it's still atomic.
>You write the 8 or 16 bit in a single step, but the other bits of the
>same 32bit memory location are loaded into a register as well and
>masked.

True.  I think I expressed myself badly referring to it as "not atomic".

>Note that this is semanticaly in no way different from a CPU loading
>a whole cacheline to change a single byte which is what every modern
>system does.

Which may or may not provide hardware interlocking to support multiple
CPUs updating adjacent memory.  The load/mask/store situation definitely
needs explicit interlocks.

Maybe what I should say is that in a threaded or multi-CPU environment,
updating any variable without locks requires intimate knowledge of how
your toolchain lays out storage and what the system coherency boundaries
are.  To explain further, say I have two variables:
        short   foo, bar;
If the toolchain happens to pack them into the same longword on an
Alpha and doesn't use the BWL-extension instructions then I can't
update 'foo' in one thread and 'bar' in a different thread without
locks.  OTOH, if 'foo' and 'bar' are in different cache lines, then
you don't need locks in any architecture.

Peter
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