Hi,
There's an idea for optimizing cache line access through object alignment
tricks in the attached mail. Feedback would be valu[able|ed].
BMS
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On Tue, Jun 24, 2003 at 09:25:43AM -0700, Matthew Dillon wrote:
[..]
> the optimized values are going to be so small (probably not even
> measureable) that it isn't worth doing.
Ok. Tweaking page coloring viz other architectures is a bikeshed. In the
absence of numbers it was necessary to test the idea. Moving swiftly on...
> If you want to find something to optimize, then cache-line alignment
> of data structures and ensuring that multiple data structures
> (such as mutexes) which are potentially used by different cpus do
> not share the same cache line is going to reap far greater benefits
> then messing around with the page coloring algorithm.
Now *that* is an interesting problem, and extremely difficult to crack, at
least for the entire kernel.
It would require a map of every instance of such a shared structure in
terms of its location within each page. In the case of dynamically-allocated
structures such as the softc for a character device, it is even harder to
deterministically calculate the location of a mutex member of such a softc
in memory. Correct me if I'm wrong here?
Would the workaround, then, not be to modify the mtx_*() set of functions
to use a zone allocator, whose allocation function could then be tuned to
allocate the lock structure which is frobbed by the atomic_*() functions
on separate cache lines?
BMS
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