:Depends on of the pins are negative logic, now doesn't it :-)
:
:And most Parallel ports I've measured clock in at about 3.3V.
:
:Warner
That sounds about right. I found a web page with the
circuit for a TTL output.
http://www.play-hookey.com/digital/electronics/ttl_gates.html
If you go down to the bottom you'll see the circuit. A TTL 'high'
is +5V through a 130 ohm resistor through a transitor (0.7V drop),
through a diode (another 0.7V drop) = 5 - 1.4 = 3.6V, but it's
actually less because there is current through the transistor,
causing an additional drop through the 130ohm resistor.
The real problem is the 130 ohm resistor. Each 1 mA you pull on
the output will drop the voltage another 0.13V, which means you can't
pull much current out of the output (and also that the output is nowhere
near 5 volts even if you don't pull any current out of it).
A TTL output is much better pulling to ground (sinking current rather
then sourcing it). As you can see, when the output is a zero the
bottom transistor is turned on and that is basically a direct
connection to ground through a 0.7V drop, with no resistor (though
there is an equivalent resistance due to the transitor), so
TTL can pull down to 0.7V or so, usually at least 20mA.
-
Now, if this were a CMOS output you basically have two symmetrical
FETs:
http://www.play-hookey.com/digital/electronics/cmos_gates.html
Which have an equivalent resistance of 50 ohms typically (well, the
web page says 200 ohms but I think it's more around 50 for HCMOS).
So a CMOS 1 is essentially 50 ohms to +V and a CMOS 0 is essentially
50 ohms to ground. This is the nice thing about CMOS... the lowest
voltage is basically ground (not 0.7V), and the highest output voltage
is basically +V (e.g. 5V rather then 3.3-3.6V).
But a parallel port output is not a [H]CMOS output, it's a TTL output,
which makes it a very poor power source.
-Matt
Matthew Dillon
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